Patents by Inventor Akash V. Giri
Akash V. Giri has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240070075Abstract: A lower-level cache managing cross-core invalidation (XI) snapshots in a shared-memory multiprocessing system, wherein the management of XI snapshots reduces an amount of required snapshots while allowing shared lower-level caches, comprising: the lower-level cache maintaining respective response sync state for at least one processor in a plurality of processors signifying that a line may have been changed by another processor since last fetched by a requesting processor.Type: ApplicationFiled: August 23, 2022Publication date: February 29, 2024Inventors: Richard Joseph Branciforte, Gregory William Alexander, Timothy Bronson, Deanna Postles Dunn Berger, Akash V. Giri, Aaron Tsai
-
Patent number: 11907132Abstract: A method for managing designated authority status in a cache line includes identifying an initial designated authority (DA) member cache for a cache line, transferring DA status from the initial DA member cache to a new DA member cache, determining whether the new DA member cache is active, indicating a final state of the initial DA cache responsive to determining that the new DA member cache is active, and overriding a DA state in a cache control structure in a directory. A method for managing cache accesses during a designated authority transfer includes receiving a designated authority (DA) status transfer request, receiving an indication that a first cache will invalidate its copy of the cache line, allowing a second cache to assume DA status for the cache line, and denying access to the first cache's copy of the cache line until invalidation by the first cache is complete.Type: GrantFiled: March 23, 2022Date of Patent: February 20, 2024Assignee: International Business Machines CorporationInventors: Jason D Kohl, Gregory William Alexander, Timothy Bronson, Akash V. Giri, Winston Herring
-
Publication number: 20230305966Abstract: A method for managing designated authority status in a cache line includes identifying an initial designated authority (DA) member cache for a cache line, transferring DA status from the initial DA member cache to a new DA member cache, determining whether the new DA member cache is active, indicating a final state of the initial DA cache responsive to determining that the new DA member cache is active, and overriding a DA state in a cache control structure in a directory. A method for managing cache accesses during a designated authority transfer includes receiving a designated authority (DA) status transfer request, receiving an indication that a first cache will invalidate its copy of the cache line, allowing a second cache to assume DA status for the cache line, and denying access to the first cache’s copy of the cache line until invalidation by the first cache is complete.Type: ApplicationFiled: March 23, 2022Publication date: September 28, 2023Inventors: Jason D. Kohl, Gregory William Alexander, Timothy Bronson, Akash V. Giri, Winston Herring
-
Patent number: 10248555Abstract: Methods and apparatus for managing an effective address table (EAT) in a multi-slice processor including receiving, from an instruction sequence unit, a next-to-complete instruction tag (ITAG); obtaining, from the EAT, a first ITAG from a tail-plus-one EAT row, wherein the EAT comprises a tail EAT row that precedes the tail-plus-one EAT row; determining, based on a comparison of the next-to-complete ITAG and the first ITAG, that the tail EAT row has completed; and retiring the tail EAT row based on the determination.Type: GrantFiled: May 31, 2016Date of Patent: April 2, 2019Assignee: International Business Machines CorporationInventors: Akash V. Giri, David S. Levitan, Mehul Patel, Albert J. Van Norstrand, Jr.
-
Patent number: 10241905Abstract: Methods and apparatus for managing an effective address table (EAT) in a multi-slice processor including receiving, from an instruction sequence unit, a next-to-complete instruction tag (ITAG); obtaining, from the EAT, a first ITAG from a tail-plus-one EAT row, wherein the EAT comprises a tail EAT row that precedes the tail-plus-one EAT row; determining, based on a comparison of the next-to-complete ITAG and the first ITAG, that the tail EAT row has completed; and retiring the tail EAT row based on the determination.Type: GrantFiled: July 27, 2016Date of Patent: March 26, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Akash V. Giri, David S. Levitan, Mehul Patel, Albert J. Van Norstrand, Jr.
-
Patent number: 9934041Abstract: A method comprises identifying a number of branches (Nb) and a number of iterations (Ni) in a loop in an instruction stream, generating a number of forward branches until the number of forward branches equals Nb, generating a non-branch instruction in between the forward branch instruction, recording in a memory, instruction stream generated and a history of each branch, an associated target address of each branch, and whether the branch is a taken branch or a not taken branch, determining whether a loop iterator number (i) is less than Ni?1, generating a backward branch with a target address which is greater than or equal to the start address and is lesser than the current address responsive to determining that (i) is less than Ni, and recording in the memory, a branch instruction of the generated backward branch and the associated target address of the backward branch.Type: GrantFiled: July 1, 2015Date of Patent: April 3, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Narasimha R. Adiga, Jatin Bhartia, Akash V. Giri, Matthias Heizmann
-
Publication number: 20170344378Abstract: Methods and apparatus for managing an effective address table (EAT) in a multi-slice processor including receiving, from an instruction sequence unit, a next-to-complete instruction tag (ITAG); obtaining, from the EAT, a first ITAG from a tail-plus-one EAT row, wherein the EAT comprises a tail EAT row that precedes the tail-plus-one EAT row; determining, based on a comparison of the next-to-complete ITAG and the first ITAG, that the tail EAT row has completed; and retiring the tail EAT row based on the determination.Type: ApplicationFiled: July 27, 2016Publication date: November 30, 2017Inventors: AKASH V. GIRI, DAVID S. LEVITAN, MEHUL PATEL, ALBERT J. VAN NORSTRAND, JR.
-
Publication number: 20170344469Abstract: Methods and apparatus for managing an effective address table (EAT) in a multi-slice processor including receiving, from an instruction sequence unit, a next-to-complete instruction tag (ITAG); obtaining, from the EAT, a first ITAG from a tail-plus-one EAT row, wherein the EAT comprises a tail EAT row that precedes the tail-plus-one EAT row; determining, based on a comparison of the next-to-complete ITAG and the first ITAG, that the tail EAT row has completed; and retiring the tail EAT row based on the determination.Type: ApplicationFiled: May 31, 2016Publication date: November 30, 2017Inventors: AKASH V. GIRI, DAVID S. LEVITAN, MEHUL PATEL, ALBERT J. VAN NORSTRAND, Jr.
-
Patent number: 9760462Abstract: Embodiments relate to testing memory write operations. An aspect includes detecting a first write operation to a set of “n” divisions in a memory table, and defining a selected set of entries of an optimization checking table corresponding to the set of “n” divisions of the memory table. The aspect includes determining that at least one selected entry of the selected set of entries is not among an optimal set of entries of the checking table. The aspect further includes determining whether to generate an optimization error or to end an optimization analysis of the first write operation without generating the optimization error by comparing the first time stamps of one or both of the at least one selected entry and one or more optimal entries of the optimal set of entries to a temporal window defined by a predetermined duration.Type: GrantFiled: September 30, 2014Date of Patent: September 12, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Narasimha R. Adiga, Jatin Bhartia, Akash V. Giri, Matthias D. Heizmann
-
Patent number: 9733946Abstract: A method comprises identifying a number of branches (Nb) and a number of iterations (Ni) in a loop in an instruction stream, generating a number of forward branches until the number of forward branches equals Nb, generating a non-branch instruction in between the forward branch instruction, recording in a memory, instruction stream generated and a history of each branch, an associated target address of each branch, and whether the branch is a taken branch or a not taken branch, determining whether a loop iterator number (i) is less than Ni?1, generating a backward branch with a target address which is greater than or equal to the start address and is lesser than the current address responsive to determining that (i) is less than Ni, and recording in the memory, a branch instruction of the generated backward branch and the associated target address of the backward branch.Type: GrantFiled: December 9, 2016Date of Patent: August 15, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Narasimha R. Adiga, Jatin Bhartia, Akash V. Giri, Matthias Heizmann
-
Publication number: 20170083342Abstract: A method comprises identifying a number of branches (Nb) and a number of iterations (Ni) in a loop in an instruction stream, generating a number of forward branches until the number of forward branches equals Nb, generating a non-branch instruction in between the forward branch instruction, recording in a memory, instruction stream generated and a history of each branch, an associated target address of each branch, and whether the branch is a taken branch or a not taken branch, determining whether a loop iterator number (i) is less than Ni?1, generating a backward branch with a target address which is greater than or equal to the start address and is lesser than the current address responsive to determining that (i) is less than Ni, and recording in the memory, a branch instruction of the generated backward branch and the associated target address of the backward branch.Type: ApplicationFiled: December 9, 2016Publication date: March 23, 2017Inventors: Narasimha R. Adiga, Jatin Bhartia, Akash V. Giri, Matthias Heizmann
-
Patent number: 9547495Abstract: A method comprises identifying a number of branches (Nb) and a number of iterations (Ni) in a loop in an instruction stream, generating a number of forward branches until the number of forward branches equals Nb, generating a non-branch instruction in between the forward branch instruction, recording in a memory, instruction stream generated and a history of each branch, an associated target address of each branch, and whether the branch is a taken branch or a not taken branch, determining whether a loop iterator number (i) is less than Ni?1, generating a backward branch with a target address which is greater than or equal to the start address and is lesser than the current address responsive to determining that (i) is less than Ni, and recording in the memory, a branch instruction of the generated backward branch and the associated target address of the backward branch.Type: GrantFiled: March 30, 2016Date of Patent: January 17, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Narasimha R. Adiga, Jatin Bhartia, Akash V. Giri, Matthias Heizmann
-
Publication number: 20170003970Abstract: A method comprises identifying a number of branches (Nb) and a number of iterations (Ni) in a loop in an instruction stream, generating a number of forward branches until the number of forward branches equals Nb, generating a non-branch instruction in between the forward branch instruction, recording in a memory, instruction stream generated and a history of each branch, an associated target address of each branch, and whether the branch is a taken branch or a not taken branch, determining whether a loop iterator number (i) is less than Ni?1, generating a backward branch with a target address which is greater than or equal to the start address and is lesser than the current address responsive to determining that (i) is less than Ni, and recording in the memory, a branch instruction of the generated backward branch and the associated target address of the backward branch.Type: ApplicationFiled: July 1, 2015Publication date: January 5, 2017Inventors: Narasimha R. Adiga, Jatin Bhartia, Akash V. Giri, Matthias Heizmann
-
Publication number: 20170003968Abstract: A method comprises identifying a number of branches (Nb) and a number of iterations (Ni) in a loop in an instruction stream, generating a number of forward branches until the number of forward branches equals Nb, generating a non-branch instruction in between the forward branch instruction, recording in a memory, instruction stream generated and a history of each branch, an associated target address of each branch, and whether the branch is a taken branch or a not taken branch, determining whether a loop iterator number (i) is less than Ni?1, generating a backward branch with a target address which is greater than or equal to the start address and is lesser than the current address responsive to determining that (i) is less than Ni, and recording in the memory, a branch instruction of the generated backward branch and the associated target address of the backward branch.Type: ApplicationFiled: March 30, 2016Publication date: January 5, 2017Inventors: Narasimha R. Adiga, Jatin Bhartia, Akash V. Giri, Matthias Heizmann
-
Patent number: 9378020Abstract: Embodiments relate to asynchronous lookahead hierarchical branch prediction. An aspect includes a computer-implemented method for asynchronous lookahead hierarchical branch prediction using a second-level branch target buffer. The method includes receiving a search request to locate branch prediction information associated with a search address. The method further includes searching, by a processing circuit, for an entry corresponding to the search request in a first-level branch target buffer. The method also includes, based on failing to locate a matching entry in the first-level branch target buffer corresponding to the search request, initiating, by the processing circuit, a secondary search to locate entries in the second-level branch target buffer having a memory region corresponding to the search request. The method additionally includes, based on locating the entries in the second-level branch target buffer, performing a bulk transfer of the entries from the second-level branch target buffer.Type: GrantFiled: September 30, 2014Date of Patent: June 28, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: James J. Bonanno, Akash V. Giri, Ulrich Mayer, Brian R. Prasky
-
Patent number: 9304883Abstract: Embodiments relate to testing memory write operations. An aspect includes detecting a first write operation to a set of “n” divisions in a memory table, and defining a selected set of entries of an optimization checking table corresponding to the set of “n” divisions of the memory table. The aspect includes determining that at least one selected entry of the selected set of entries is not among an optimal set of entries of the checking table. The aspect further includes determining whether to generate an optimization error or to end an optimization analysis of the first write operation without generating the optimization error by comparing the first time stamps of one or both of the at least one selected entry and one or more optimal entries of the optimal set of entries to a temporal window defined by a predetermined duration.Type: GrantFiled: April 25, 2014Date of Patent: April 5, 2016Assignee: International Business Machines CorporationInventors: Narasimha R. Adiga, Jatin Bhartia, Akash V. Giri, Matthias D. Heizmann
-
Patent number: 9298465Abstract: Embodiments relate to asynchronous lookahead hierarchical branch prediction. An aspect includes a system for asynchronous lookahead hierarchical branch prediction. The system includes a first-level branch target buffer and a second-level branch target buffer coupled to a processing circuit. The processing circuit is configured to perform a method. The method includes receiving a search request to locate branch prediction information associated with a search address, and searching for an entry corresponding to the search request in the first-level branch target buffer. Based on failing to locate a matching entry in the first-level branch target buffer corresponding to the search request, a secondary search is initiated to locate entries in the second-level branch target buffer having a memory region corresponding to the search request. Based on locating the entries in the second-level branch target buffer, a bulk transfer of the entries is performed from the second-level branch target buffer.Type: GrantFiled: June 15, 2012Date of Patent: March 29, 2016Assignee: International Business Machines CorporationInventors: James J. Bonanno, Akash V. Giri, Ulrich Mayer, Brian R. Prasky
-
Publication number: 20150309904Abstract: Embodiments relate to testing memory write operations. An aspect includes detecting a first write operation to a set of “n” divisions in a memory table, and defining a selected set of entries of an optimization checking table corresponding to the set of “n” divisions of the memory table. The aspect includes determining that at least one selected entry of the selected set of entries is not among an optimal set of entries of the checking table. The aspect further includes determining whether to generate an optimization error or to end an optimization analysis of the first write operation without generating the optimization error by comparing the first time stamps of one or both of the at least one selected entry and one or more optimal entries of the optimal set of entries to a temporal window defined by a predetermined duration.Type: ApplicationFiled: April 25, 2014Publication date: October 29, 2015Applicant: International Business Machines CorporationInventors: Narasimha R. Adiga, Jatin Bhartia, Akash V. Giri, Matthias D. Heizmann
-
Publication number: 20150309905Abstract: Embodiments relate to testing memory write operations. An aspect includes detecting a first write operation to a set of “n” divisions in a memory table, and defining a selected set of entries of an optimization checking table corresponding to the set of “n” divisions of the memory table. The aspect includes determining that at least one selected entry of the selected set of entries is not among an optimal set of entries of the checking table. The aspect further includes determining whether to generate an optimization error or to end an optimization analysis of the first write operation without generating the optimization error by comparing the first time stamps of one or both of the at least one selected entry and one or more optimal entries of the optimal set of entries to a temporal window defined by a predetermined duration.Type: ApplicationFiled: September 30, 2014Publication date: October 29, 2015Inventors: Narasimha R. Adiga, Jatin Bhartia, Akash V. Giri, Matthias D. Heizmann
-
Publication number: 20150019848Abstract: Embodiments relate to asynchronous lookahead hierarchical branch prediction. An aspect includes a computer-implemented method for asynchronous lookahead hierarchical branch prediction using a second-level branch target buffer. The method includes receiving a search request to locate branch prediction information associated with a search address. The method further includes searching, by a processing circuit, for an entry corresponding to the search request in a first-level branch target buffer. The method also includes, based on failing to locate a matching entry in the first-level branch target buffer corresponding to the search request, initiating, by the processing circuit, a secondary search to locate entries in the second-level branch target buffer having a memory region corresponding to the search request. The method additionally includes, based on locating the entries in the second-level branch target buffer, performing a bulk transfer of the entries from the second-level branch target buffer.Type: ApplicationFiled: September 30, 2014Publication date: January 15, 2015Inventors: James J. Bonanno, Akash V. Giri, Ulrich Mayer, Brian R. Prasky