Abstract: An active I/Q generator circuit comprises an input node for receiving a reference oscillation signal. The circuit has an I-output and a Q-output for respectively outputting an I-signal and a Q-signal. A first active component is electrically coupled to the input node and arranged to amplify the reference oscillation signal and to output an amplified reference oscillation signal. A second active component is electrically coupled to the first active component to receive the amplified reference oscillation signal. The second active component is arranged to generate, based on the amplified reference oscillation signal, an in-phase signal and a, with respect to the in-phase signal, phase shifted signal, the second active component electrically coupled to the in-phase signal output for providing the in-phase signal and electrically coupled to the quadrature-phase output for providing the phase-shifted signal.

Abstract: A receiver system which may be implemented in an integrated circuit device and suitable for use in automotive radar systems such as collision avoidance systems, includes self test circuitry whereby a local oscillator test signal is generated by an on-board frequency multiplier and mixed in a down-conversion mixer with an RF test signal. The RF test signal is generated on the device by up-conversion of an externally generated low-frequency test signal with the local oscillator test signal. Baseband components may also be checked using test signals of suitable frequency divided down from the local oscillator test signal by a programmable frequency divider. This self test arrangement obviates any need for applying externally generated RF test signals to the IC device.

Abstract: An active I/Q generator circuit comprises an input node for receiving a reference oscillation signal. The circuit has an I-output and a Q-output for respectively outputting an I-signal and a Q-signal. A first active component is electrically coupled to the input node and arranged to amplify the reference oscillation signal and to output an amplified reference oscillation signal. A second active component is electrically coupled to the first active component to receive the amplified reference oscillation signal. The second active component is arranged to generate, based on the amplified reference oscillation signal, an in-phase signal and a, with respect to the in-phase signal, phase shifted signal, the second active component electrically coupled to the in-phase signal output for providing the in-phase signal and electrically coupled to the quadrature-phase output for providing the phase-shifted signal.

Abstract: The invention relates to a Frequency Divider Circuit for dividing an input RF signal to a frequency divided RF signal. The circuit comprises a RF pair, a switching-quad pair coupled in series with a transimpedance amplifier and a double pair of emitter followers. The circuit comprises coupling elements for providing first DC paths to first amplifier paths of the RF pair and for providing second DC paths to second amplifier paths of the series arrangement of the switching-quad pair and the transimpedance amplifier. The first DC paths are independent of the second DC paths. RF connections are provided to couple the first and the second amplifier paths for transferring a signal from the first amplifier paths to the second amplifier paths.

Abstract: The invention relates to a Frequency Divider Circuit for dividing an input RF signal to a frequency divided RF signal. The circuit comprises a RF pair, a switching-quad pair coupled in series with a transimpedance amplifier and a double pair of emitter followers. The circuit comprises coupling elements for providing first DC paths to first amplifier paths of the RF pair and for providing second DC paths to second amplifier paths of the series arrangement of the switching-quad pair and the transimpedance amplifier. The first DC paths are independent of the second DC paths. RF connections are provided to couple the first and the second amplifier paths for transferring a signal from the first amplifier paths to the second amplifier paths.

Abstract: A phase switchable bistable memory device comprising a bistable memory component and a phase switching component is described. The bistable memory component comprises a bistable memory stage arranged to receive an input signal and a state transition stage arranged to receive a state transition signal and to cause the bistable memory stage to capture a logical state of the received input signal upon a transition from a first logical state of the state transition signal to a second logical state of the state transition signal. The phase switching component is arranged to receive a clock input signal and a phase control signal, and to output the state transition signal comprising transitions between logical states corresponding to transitions between logical states of the clock input signal and comprising a phase relative to the clock input signal based at least partly on the received phase control signal.

Abstract: An integrated circuit comprises frequency generation circuitry for controlling a frequency source for an automotive radar system. The frequency generation circuitry comprises a Phase Locked Loop (PLL) arranged to generate a control signal for controlling the frequency source, a fractional-N divider located within a feedback loop of the PLL, and frequency pattern control logic operably coupled to the fractional-N divider and arranged to control the fractional-N divider, by way of a frequency control signal, such that the PLL generates a Frequency Modulated Continuous Wave (FMCW) control signal.

Abstract: An integrated circuit comprises frequency generation circuitry for controlling a frequency source for an automotive radar system. The frequency generation circuitry comprises a Phase Locked Loop (PLL) arranged to generate a control signal for controlling the frequency source, a fractional-N divider located within a feedback loop of the PLL, and frequency pattern control logic operably coupled to the fractional-N divider and arranged to control the fractional-N divider, by way of a frequency control signal, such that the PLL generates a Frequency Modulated Continuous Wave (FMCW) control signal.