Patents by Inventor Akella Sastry

Akella Sastry has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10860766
    Abstract: An example method of implementing an application for a system-on-chip (SOC) having a data processing engine (DPE) array includes determining a graph representation of the application, the graph representation including nodes representing kernels of the application and edges representing communication between the kernels, mapping, based on the graph, the kernels onto DPEs of the DPE array and data structures of the kernels onto memory in the DPE array, routing communication channels between DPEs and circuitry of the application configured in programmable logic of the SOC, and generating implementation data for programming the SOC to implement the application based on results of the mapping and the routing.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: December 8, 2020
    Assignee: XILINX, INC.
    Inventors: Mukund Sivaraman, Shail Aditya Gupta, Akella Sastry, Rishi Surendran, Philip B. James-Roxby, Samuel R. Bayliss, Vinod K. Kathail, Ajit K. Agarwal, Ralph D. Wittig
  • Publication number: 20200371759
    Abstract: For an application specifying a software portion for implementation within a data processing engine (DPE) array of a device and a hardware portion having High-Level Synthesis (HLS) kernels for implementation within programmable logic (PL) of the device, a first interface solution is generated that maps logical resources used by the software portion to hardware resources of an interface block coupling the DPE array and the PL. A connection graph specifying connectivity among the HLS kernels and nodes of the software portion to be implemented in the DPE array; and, a block diagram based on the connection graph and the HLS kernels are generated. The block diagram is synthesizable. An implementation flow is performed on the block diagram based on the first interface solution. The software portion of the application is compiled for implementation in one or more DPEs of the DPE array.
    Type: Application
    Filed: May 23, 2019
    Publication date: November 26, 2020
    Applicant: Xilinx, Inc.
    Inventors: Akella Sastry, Vinod K. Kathail, L. James Hwang, Shail Aditya Gupta, Vidhumouli Hunsigida, Siddarth Rele
  • Publication number: 20200372200
    Abstract: An example method of implementing an application for a system-on-chip (SOC) having a data processing engine (DPE) array includes determining a graph representation of the application, the graph representation including nodes representing kernels of the application and edges representing communication between the kernels, mapping, based on the graph, the kernels onto DPEs of the DPE array and data structures of the kernels onto memory in the DPE array, routing communication channels between DPEs and circuitry of the application configured in programmable logic of the SOC, and generating implementation data for programming the SOC to implement the application based on results of the mapping and the routing.
    Type: Application
    Filed: May 23, 2019
    Publication date: November 26, 2020
    Applicant: Xilinx, Inc.
    Inventors: Mukund Sivaraman, Shail Aditya Gupta, Akella Sastry, Rishi Surendran, Philip B. James-Roxby, Samuel R. Bayliss, Vinod K. Kathail, Ajit K. Agarwal, Ralph D. Wittig
  • Publication number: 20200371761
    Abstract: Examples herein describe techniques for generating dataflow graphs using source code for defining kernels and communication links between those kernels. In one embodiment, the graph is formed using nodes (e.g., kernels) which are communicatively coupled by edges (e.g., the communication links between the kernels). A compiler converts the source code into a bit stream and/or binary code which configure a heterogeneous processing system of a SoC to execute the graph. The compiler uses the graph expressed in source code to determine where to assign the kernels in the heterogeneous processing system. Further, the compiler can select the specific communication techniques to establish the communication links between the kernels and whether synchronization should be used in a communication link. Thus, the programmer can express the dataflow graph at a high-level (using source code) without understanding about how the operator graph is implemented using the heterogeneous hardware in the SoC.
    Type: Application
    Filed: May 23, 2019
    Publication date: November 26, 2020
    Applicant: Xilinx, Inc.
    Inventors: Shail Aditya Gupta, Samuel R. Bayliss, Vinod K. Kathail, Ralph D. Wittig, Philip B. James-Roxby, Akella Sastry
  • Patent number: 10228919
    Abstract: One embodiment of the present invention sets forth a technique for reducing sign-extension instructions (SEIs) included in a computer program, the technique involves receiving intermediate code that is associated with the computer program and includes a first SEI that is included in a loop structure within the computer program, determining that the first SEI is eligible to be moved outside of the loop structure, inserting into a preheader of the loop a second SEI that, when executed by a processor, promotes an original value targeted by the first SEI from a smaller type to a larger type, and replacing the first SEI with one or more intermediate instructions that are eligible for additional compiler optimizations.
    Type: Grant
    Filed: October 26, 2012
    Date of Patent: March 12, 2019
    Assignee: NVIDIA CORPORATION
    Inventors: Akella Sastry, Yuan Lin
  • Publication number: 20070006192
    Abstract: As described herein, an intermediate representation of a source code file may be used to explicitly express exception handling control flow prior to generating object code for the source code. As further described herein, a single uniform set of instructions of the intermediate representation may be used for expressing multiple different exception handling mechanisms related to multiple different programming languages. The intermediate form of the exception handling instructions may be generated by translating an intermediate language representation of the source code file. Representations of the source code in multiple different intermediate languages may be translated to a single uniform set of instructions of the intermediate representation. The intermediate form of the exception handling instructions may then be used by software development tools for such tasks as code generation, code optimization, code analysis etc.
    Type: Application
    Filed: August 15, 2006
    Publication date: January 4, 2007
    Applicant: Microsoft Corporation
    Inventors: Vinod Grover, Akella Sastry