Patents by Inventor Akeno Ito

Akeno Ito has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SEMICONDUCTOR DEVICE HAVING READ DATA BUSES AND WRITE DATA BUSES
    Publication number: 20240112725
    Abstract: An apparatus that includes: a plurality of first data amplifiers arranged in line in a first direction; a plurality of first read data buses each coupled to a corresponding one of the plurality of first data amplifiers, the plurality of first read data buses having different lengths one another; and a plurality of first write data buses each coupled to the corresponding one of the plurality of first data amplifiers, the plurality of first write data buses having different lengths one another. The plurality of first read data buses and the plurality of first write data buses are alternately arranged in parallel in a second direction vertical to the first direction. The plurality of first read data buses are arranged in longest order and the plurality of first write data buses are arranged in shortest order.
    Type: Application
    Filed: September 29, 2022
    Publication date: April 4, 2024
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: AKENO ITO, MAMORU NISHIZAKI
  • Semiconductor device equipped with column decoder circuit
    Patent number: 11715522
    Abstract: Disclosed herein is an apparatus that includes a driver circuit including a plurality of first transistors arranged in a first direction; a control circuit including a plurality of second transistors arranged in parallel to the plurality of first transistors, each of the plurality of second transistors being coupled to control an associated one of the first transistors; and a power gating circuit arranged between the driver circuit and the control circuit, the power gating circuit being configured to supply a first power potential to each of the plurality of first transistors.
    Type: Grant
    Filed: June 25, 2021
    Date of Patent: August 1, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Akeno Ito, Takayori Hamada, Mamoru Nishizaki
  • SEMICONDUCTOR DEVICE EQUIPPED WITH COLUMN DECODER CIRCUIT
    Publication number: 20220415397
    Abstract: Disclosed herein is an apparatus that includes a driver circuit including a plurality of first transistors arranged in a first direction; a control circuit including a plurality of second transistors arranged in parallel to the plurality of first transistors, each of the plurality of second transistors being coupled to control an associated one of the first transistors; and a power gating circuit arranged between the driver circuit and the control circuit, the power gating circuit being configured to supply a first power potential to each of the plurality of first transistors.
    Type: Application
    Filed: June 25, 2021
    Publication date: December 29, 2022
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Akeno Ito, Takayori Hamada, Mamoru Nishizaki