Patents by Inventor Akhan Almagambetov

Akhan Almagambetov has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10306135
    Abstract: There is set forth herein a system including a camera device. In one embodiment the system is operative to perform image processing for detection of an event involving a human subject. There is set forth herein in one embodiment, a camera equipped system employed for fall detection.
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: May 28, 2019
    Assignee: Syracuse University
    Inventors: Senem Velipasalar, Mauricio Casares, Akhan Almagambetov
  • Patent number: 10275219
    Abstract: A Field-Programmable Gate Array (FPGA) implementation of a multiplier topology can provide a considerable increase in computation performance and cost benefit as compared to other approaches, particularly for large bit widths (e.g., for multiplication of large-bit numbers). A lack of sufficient input/output (I/O) ports on the FPGA for a particular bit width can be remedied by implementing large-bit number multiplications in a bit-serial fashion. The bit-serial multiplier topologies described herein can provide a relatively small footprint as compared to other approaches. An FPGA-implemented bit-serial multiplier can improve operation of a computing system, for example, by offloading binary multiplication operations from a general-purpose processor.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: April 30, 2019
    Assignee: Embry-Riddle Aeronautical University, Inc.
    Inventors: Akhan Almagambetov, Holly Renee Ross
  • Publication number: 20180129475
    Abstract: A Field-Programmable Gate Array (FPGA) implementation of a multiplier topology can provide a considerable increase in computation performance and cost benefit as compared to other approaches, particularly for large bit widths (e.g., for multiplication of large-bit numbers). A lack of sufficient input/output (I/O) ports on the FPGA for a particular bit width can be remedied by implementing large-bit number multiplications in a bit-serial fashion. The bit-serial multiplier topologies described herein can provide a relatively small footprint as compared to other approaches. An FPGA-implemented bit-serial multiplier can improve operation of a computing system, for example, by offloading binary multiplication operations from a general-purpose processor.
    Type: Application
    Filed: November 8, 2017
    Publication date: May 10, 2018
    Inventors: Akhan Almagambetov, Holly Renee Ross
  • Publication number: 20180007257
    Abstract: There is set forth herein a system including a camera device. In one embodiment the system is operative to perform image processing for detection of an event involving a human subject. There is set forth herein in one embodiment, a camera equipped system employed for fall detection.
    Type: Application
    Filed: February 13, 2017
    Publication date: January 4, 2018
    Inventors: Senem VELIPASALAR, Mauricio CASARES, Akhan ALMAGAMBETOV
  • Patent number: 9571723
    Abstract: There is set forth herein a system including a camera device. In one embodiment the system is operative to perform image processing for detection of an event involving a human subject. There is set forth herein in one embodiment, a camera equipped system employed for fall detection.
    Type: Grant
    Filed: November 16, 2012
    Date of Patent: February 14, 2017
    Assignee: National Science Foundation
    Inventors: Senem Velipasalar, Akhan Almagambetov, Mauricio Casares