Patents by Inventor Akhil Garg
Akhil Garg has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11953749Abstract: The present disclosure provides an intermittently bonded optical fibre ribbon. The intermittently bonded optical fibre ribbon includes a plurality of optical fibres such that adjacent optical fibre of the plurality of optical fibres is bonded intermittently along the length by a plurality of bonds. The plurality of bonds is defined by a plurality of colours. The plurality of bonds may form a predefined pattern. The predefined pattern may be used for identification of the intermittently bonded optical fibre ribbon.Type: GrantFiled: December 31, 2020Date of Patent: April 9, 2024Assignee: Sterlite Technologies LimitedInventors: Hemanth Kondapalli, Atulkumar Mishra, Akhil Garg
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Publication number: 20240085028Abstract: A cooking appliance comprises an outer frame surface defining a cooktop and the cooktop defines an outlet port. An inner frame surface defines a heating cavity disposed below the cooktop and within the outer frame surface. The inner frame surface defines an inlet port and a chimney extends between a first end connected to the inlet port and a second end connected to the outlet port for directing steam from the heating cavity outside of the cooking appliance. A nozzle apparatus is connected around the outlet port and includes an inner wall defining at least one aperture. The at least one aperture is oriented at an acute angle relative to the cooktop. The nozzle apparatus includes at least one post for connection to the cooktop.Type: ApplicationFiled: September 9, 2022Publication date: March 14, 2024Applicant: WHIRLPOOL CORPORATIONInventors: Lisa E. Blumenthal, Davide Bottalico, Trevor T. Carlson, Nicholas E. Crow, Kevin Dolezan, Ankur Garg, Hemlata P. Khanvilkar, Nicholas J. Kormanik, Ajit Maruti Patil, Timothy Patrick VanAntwerp, Dustin M. Walter, Akhil Haribhau Wankhede
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Patent number: 11320485Abstract: A system-on-chip (SoC) is disclosed. The SoC includes a set of input channels, a first partition including a set of output wrapper chains, a set of output channels, a second partition including a set of input wrapper chains, and an inter-partition circuit coupled between the first and second partitions. During an external test mode, the set of input channels receives input test data. The set of output wrapper chains receives and stores intermediate data that is generated based on the input test data. The inter-partition circuit receives the intermediate data from the set of output wrapper chains and generates test response data based on the intermediate data. The set of input wrapper chains receives the test response data, and provides the test response data to be captured as output test data at the set of output channels to test the inter-partition circuit.Type: GrantFiled: December 31, 2020Date of Patent: May 3, 2022Assignee: NXP USA, Inc.Inventors: Akhil Garg, Sahil Jain
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Patent number: 11300741Abstract: An intermittently bonded optical fibre ribbon includes a plurality of optical fibres. The plurality of optical fibres is defined by at least two adjacent central optical fibers, a first plurality of optical fibers and a second plurality of fibers. The at least two adjacent central optical fibers are sandwiched between the first plurality of optical fibers and the second plurality of optical fibers. The at least two adjacent central optical fibers are fully bonded along length of the at least two central fibres. The first plurality of fibers and the second plurality of optical fibers are bonded partially along non-central length of the plurality of optical fibres.Type: GrantFiled: December 31, 2020Date of Patent: April 12, 2022Assignee: STERLITE TECHNOLOGIES LIMITEDInventors: Kishore Sahoo, Swapnil Sharma, Akhil Garg
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Publication number: 20210286143Abstract: The present disclosure provides an intermittently bonded optical fibre ribbon. The intermittently bonded optical fibre ribbon includes a plurality of optical fibres such that adjacent optical fibre of the plurality of optical fibres is bonded intermittently along the length by a plurality of bonds. The plurality of bonds is defined by a plurality of colours. The plurality of bonds may form a predefined pattern. The predefined pattern may be used for identification of the intermittently bonded optical fibre ribbon.Type: ApplicationFiled: December 31, 2020Publication date: September 16, 2021Inventors: Hemanth Kondapalli, Atulkumar Mishra, Akhil Garg
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Publication number: 20210271040Abstract: An intermittently bonded optical fibre ribbon includes a plurality of optical fibres. The plurality of optical fibres is defined by at least two adjacent central optical fibers, a first plurality of optical fibers and a second plurality of fibers. The at least two adjacent central optical fibers are sandwiched between the first plurality of optical fibers and the second plurality of optical fibers. The at least two adjacent central optical fibers are fully bonded along length of the at least two central fibres. The first plurality of fibers and the second plurality of optical fibers are bonded partially along non-central length of the plurality of optical fibres.Type: ApplicationFiled: December 31, 2020Publication date: September 2, 2021Inventors: Kishore Sahoo, Swapnil Sharma, Akhil Garg
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Publication number: 20210041655Abstract: The present disclosure provides an optical fibre cable. The optical fibre cable includes a plurality of buffer tubes and a plurality of interstitial fillers in spaces between the plurality of buffer tubes. The plurality of interstitial fillers is arranged in spaces between the plurality of buffer tubes. The optical fibre cable may include a plurality of water swellable yarns. There is an optical fibre ribbon stack including a plurality of optical fibre ribbons. The plurality of optical fibre ribbons are stacked to form the optical fibre ribbon stack. The present disclosure provides a fire retardant optical fibre cable includes the plurality of buffer tubes and one or more numbers of interstitial fillers and includes at least one of a thermal resistant water blocking tape, a fire resistant water blocking tape and a Mica tape wrapped over the core of the fire retardant optical fibre cable.Type: ApplicationFiled: August 7, 2020Publication date: February 11, 2021Inventors: Kishore Sahoo, Sravan Kumar, Atulkumar Mishra, Vikash Shukla, Akhil Garg, Hemanth Kondapalli, Mahesh Deshpande, Gahininath Shinde, Venkatesh Murthy, Pramod Marru
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Patent number: 10747922Abstract: A test circuit includes a plurality of codec logic elements arranged in a plurality of annular rings on an integrated circuit, each codec logic element configured to provide test bits to one or more respective scan chain and receive test result bits from the one or more respective scan chain. The test circuit further includes a decompressor logic arranged along at least one annular ring of the plurality of annular rings on the integrated circuit, the decompressor logic configured to provide test bits to at least one codec logic element in each annular ring. The test circuit also includes a compressor logic arranged transversely with respect to the plurality of annular rings on the integrated circuit, the compressor logic configured to receive test result bits from at least one of the plurality of codec logic elements.Type: GrantFiled: April 18, 2018Date of Patent: August 18, 2020Assignee: Cadence Design Systems, Inc.Inventors: Akhil Garg, Sahil Jain, Vivek Chickermane
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Patent number: 10222417Abstract: Embodiments relate to providing security of scan mode access and data in an integrated circuit. In embodiments, one or both of two layers of security are provided. A first layer includes requiring a complex initialization sequence to be performed in order to access scan mode. A second layer includes scrambling the scan data before it is output from the circuit under test, which prevents unauthorized persons from extracting useful information from the output scan data. Further embodiments relate to methodologies for utilizing these protection layers after manufacture of the integrated circuit and incorporating these protection layers in an integrated circuit design flow.Type: GrantFiled: November 28, 2016Date of Patent: March 5, 2019Assignee: CADENCE DESIGN SYSTEMS, INC.Inventors: Akhil Garg, Dale Meehl, Sahil Jain
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Patent number: 8527824Abstract: A system for testing multi-clock domains in an integrated circuit (IC) includes a plurality of clock sources coupled to a plurality of clock controllers. Each of the clock sources generates a fast clock associated with one of the multi-clock domains. Each of the clock controllers is configured to provide capture pulses to test one clock domain. The capture pulses provided to a clock domain are at a frequency of a fast clock associated with the clock domain. The clock controllers operate sequentially to provide the capture pulses to test the clock domains.Type: GrantFiled: January 11, 2013Date of Patent: September 3, 2013Assignee: STMicroelectronics International N.V.Inventors: Swapnil Bahl, Akhil Garg
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Patent number: 8386864Abstract: A system and method of sharing testing components for multiple embedded memories and the memory system incorporating the same are disclosed. The memory system includes multiple test controllers, multiple interface devices, a main controller, and a serial interface. The main controller is used for initializing testing of each of the dissimilar memory groups using a serial interface and local test controllers. The memory system results in reduced routing congestion and faster testing of plurality of dissimilar memories. The present disclosure further provides a programmable shared built in self-testing (BIST) architecture utilizing globally asynchronous and locally synchronous (GALS) methodology for testing multiple memories. The built in self-test (BIST) architecture includes a programmable master controller, multiple memory wrappers, and an interface. The interface can be a globally asynchronous and locally synchronous (GALS) interface.Type: GrantFiled: January 30, 2012Date of Patent: February 26, 2013Assignee: STMicroelectronics PVT. Ltd.Inventors: Prashant Dubey, Akhil Garg, Sravan Kumar Bhaskarani
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Patent number: 8381051Abstract: A system for testing multi-clock domains in an integrated circuit (IC) includes a plurality of clock sources coupled to a plurality of clock controllers. Each of the clock sources generates a fast clock associated with one of the multi-clock domains. Each of the clock controllers is configured to provide capture pulses to test one clock domain. The capture pulses provided to a clock domain are at a frequency of a fast clock associated with the clock domain. The clock controllers operate sequentially to provide the capture pulses to test the clock domains.Type: GrantFiled: June 22, 2010Date of Patent: February 19, 2013Assignee: STMicroelectronics International N.V.Inventors: Swapnil Bahl, Akhil Garg
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Patent number: 8352781Abstract: The system and method are for efficient detection and restoration of data storage array defects. The system may include a data storage subsystem, wherein the data storage subsystem includes a data storage array, read-write logic coupled to the data storage array, a parity generator for producing and storing check data during write operations to the data storage array and generating check data during read operations on the data storage array, and a parity checker for verifying the stored check data with generated check data and identifying defective data read-write elements during read operations on the data storage array. The subsystem may further include a Built-in Self Test (BIST) generator operating only on the identified defective data read-write elements for determining defective data storage elements in the defective data read-write elements, and a restoration mechanism for restoring the valid operation of data access elements containing the defective data storage elements in the data storage array.Type: GrantFiled: July 6, 2009Date of Patent: January 8, 2013Assignee: STMicroelectronics International N.V.Inventors: Akhil Garg, Prashant Dubey
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Publication number: 20120198291Abstract: A system and method of sharing testing components for multiple embedded memories and the memory system incorporating the same. The memory system includes multiple test controllers, multiple interface devices, a main controller, and a serial interface. The main controller is used for initializing testing of each of the dissimilar memory groups using a serial interface and local test controllers. The memory system results in reduced routing congestion and faster testing of plurality of dissimilar memories. The present disclosure further provides a programmable shared built in self testing (BIST) architecture utilizing globally asynchronous and locally synchronous (GALS) methodology for testing multiple memories. The built in self test (BIST) architecture includes a programmable master controller, multiple memory wrappers, and an interface. The interface can be a globally asynchronous and locally synchronous (GALS) interface.Type: ApplicationFiled: January 30, 2012Publication date: August 2, 2012Applicant: STMICROELECTRONICS PVT. LTD.Inventors: Prashant Dubey, Akhil Garg, Sravan Kumar Bhaskarani
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Patent number: 8108744Abstract: A system and method of sharing testing components for multiple embedded memories and the memory system incorporating the same. The memory system includes multiple test controllers, multiple interface devices, a main controller, and a serial interface. The main controller is used for initializing testing of each of the dissimilar memory groups using a serial interface and local test controllers. The memory system results in reduced routing congestion and faster testing of plurality of dissimilar memories. The present disclosure further provides a programmable shared built in self testing (BIST) architecture utilizing globally asynchronous and locally synchronous (GALS) methodology for testing multiple memories. The built in self test (BIST) architecture includes a programmable master controller, multiple memory wrappers, and an interface. The interface can be a globally asynchronous and locally synchronous (GALS) interface.Type: GrantFiled: August 13, 2007Date of Patent: January 31, 2012Assignee: STMicroelectronics Pvt. Ltd.Inventors: Prashant Dubey, Akhil Garg, Sravan Kumar Bhaskarani
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Publication number: 20110264971Abstract: A system for testing multi-clock domains in an integrated circuit (IC) includes a plurality of clock sources coupled to a plurality of clock controllers. Each of the clock sources generates a fast clock associated with one of the multi-clock domains. Each of the clock controllers is configured to provide capture pulses to test one clock domain. The capture pulses provided to a clock domain are at a frequency of a fast clock associated with the clock domain. The clock controllers operate sequentially to provide the capture pulses to test the clock domains.Type: ApplicationFiled: June 22, 2010Publication date: October 27, 2011Applicant: STMICROELECTRONICS PVT. LTD.Inventors: Swapnil Bahl, Akhil Garg
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Patent number: 7954017Abstract: A method of sharing testing components for multiple embedded memories and the memory system incorporating the same. The memory system includes multiple test controllers, multiple interface devices, a main controller, and a serial interface. The main controller is used for initializing testing of each of the dissimilar memory groups using a serial interface and local test controllers. The memory system results in reduced routing congestion and faster testing of plurality of dissimilar memories.Type: GrantFiled: November 28, 2006Date of Patent: May 31, 2011Assignee: STMicroelectronics Pvt. Ltd.Inventors: Amit Kashyap, Prashant Dubey, Akhil Garg
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Publication number: 20100017651Abstract: The system and method are for efficient detection and restoration of data storage array defects. The system may include a data storage subsystem, wherein the data storage subsystem includes a data storage array, read-write logic coupled to the data storage array, a parity generator for producing and storing check data during write operations to the data storage array and generating check data during read operations on the data storage array, and a parity checker for verifying the stored check data with generated check data and identifying defective data read-write elements during read operations on the data storage array. The subsystem may further include a Built-in Self Test (BIST) generator operating only on the identified defective data read-write elements for determining defective data storage elements in the defective data read-write elements, and a restoration mechanism for restoring the valid operation of data access elements containing the defective data storage elements in the data storage array.Type: ApplicationFiled: July 6, 2009Publication date: January 21, 2010Applicant: STMicroelectronics Pvt. Ltd.Inventors: Akhil Garg, Prashant Dubey
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Publication number: 20080126892Abstract: A system and method of sharing testing components for multiple embedded memories and the memory system incorporating the same. The memory system includes multiple test controllers, multiple interface devices, a main controller, and a serial interface. The main controller is used for initializing testing of each of the dissimilar memory groups using a serial interface and local test controllers. The memory system results in reduced routing congestion and faster testing of plurality of dissimilar memories. The present disclosure further provides a programmable shared built in self testing (BIST) architecture utilizing globally asynchronous and locally synchronous (GALS) methodology for testing multiple memories. The built in self test (BIST) architecture includes a programmable master controller, multiple memory wrappers, and an interface. The interface can be a globally asynchronous and locally synchronous (GALS) interface.Type: ApplicationFiled: August 13, 2007Publication date: May 29, 2008Applicant: STMICROELECTRONICS PVT. LTD.Inventors: Prashant Dubey, Akhil Garg, Sravan Kumar Bhaskarani
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Publication number: 20070162793Abstract: A method of sharing testing components for multiple embedded memories and the memory system incorporating the same. The memory system includes multiple test controllers, multiple interface devices, a main controller, and a serial interface. The main controller is used for initializing testing of each of the dissimilar memory groups using a serial interface and local test controllers. The memory system results in reduced routing congestion and faster testing of plurality of dissimilar memories.Type: ApplicationFiled: November 28, 2006Publication date: July 12, 2007Applicant: STMICROELECTRONICS PVT, LTD.Inventors: Amit Kashyap, Prashant Dubey, Akhil Garg