Patents by Inventor Akhil Langer

Akhil Langer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11677839
    Abstract: Apparatuses, systems, and techniques are directed to automatic coalescing of GPU-initiated network communications. In one method, a communication engine receives, from a shared memory application executing on a first graphics processing unit (GPU), a first communication request assigned to or having a second GPU as a destination to be processed. The communication engine determines that the first communication request satisfies a coalescing criterion and stores the first communication request in association with a group of requests that have a common property. The communication engine coalesces the group of requests into a coalesced request and transports the coalesced request to the second GPU over a network.
    Type: Grant
    Filed: June 17, 2021
    Date of Patent: June 13, 2023
    Assignee: NVIDIA Corporation
    Inventors: James Dinan, Akhil Langer, Sreeram Potluri
  • Publication number: 20220407920
    Abstract: Apparatuses, systems, and techniques are directed to automatic coalescing of GPU-initiated network communications. In one method, a communication engine receives, from a shared memory application executing on a first graphics processing unit (GPU), a first communication request assigned to or having a second GPU as a destination to be processed. The communication engine determines that the first communication request satisfies a coalescing criterion and stores the first communication request in association with a group of requests that have a common property. The communication engine coalesces the group of requests into a coalesced request and transports the coalesced request to the second GPU over a network.
    Type: Application
    Filed: June 17, 2021
    Publication date: December 22, 2022
    Inventors: James Dinan, Akhil Langer, Sreeram Potluri
  • Patent number: 11321136
    Abstract: Various embodiments are generally directed to techniques for collective operations among compute nodes in a distributed processing set, such as by utilizing ring sets and local sets of the distributed processing set. In some embodiments, a ring set may include a subset of the distributed processing set in which each compute node is connected to a network with a separate router. In various embodiments, a local set may include a subset of the distributed processing set in which each compute node is connected to a network with a common router. In one or more embodiments, each compute node in a distributed processing set may belong to one ring set and one local set.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: May 3, 2022
    Assignee: INTEL CORPORATION
    Inventor: Akhil Langer
  • Patent number: 10846245
    Abstract: Examples include a computing system having an input/output (I/O) device including a plurality of counters, each counter operating as one of a completion counter and a trigger counter, a processing device; and a memory device. The memory device stores instructions that, in response to execution by the processing device, cause the processing device to represent a plurality of triggered operations of collective communication for high-performance computing executable by the I/O device as a directed acyclic graph stored in the memory device, with triggered operations represented as vertices of the directed acyclic graph and dependencies between triggered operations represented as edges of the directed acyclic graph; traverse the directed acyclic graph using a first process to identify and mark vertices that can share a completion counter; and traverse the directed acyclic graph using a second process to assign a completion counter and a trigger counter for each vertex.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: November 24, 2020
    Assignee: Intel Corporation
    Inventors: Nusrat Islam, Gengbin Zheng, Sayantan Sur, Maria Garzaran, Akhil Langer
  • Publication number: 20190213146
    Abstract: Examples include a computing system having an input/output (I/O) device including a plurality of counters, each counter operating as one of a completion counter and a trigger counter, a processing device; and a memory device. The memory device stores instructions that, in response to execution by the processing device, cause the processing device to represent a plurality of triggered operations of collective communication for high-performance computing executable by the I/O device as a directed acyclic graph stored in the memory device, with triggered operations represented as vertices of the directed acyclic graph and dependencies between triggered operations represented as edges of the directed acyclic graph; traverse the directed acyclic graph using a first process to identify and mark vertices that can share a completion counter; and traverse the directed acyclic graph using a second process to assign a completion counter and a trigger counter for each vertex.
    Type: Application
    Filed: March 14, 2019
    Publication date: July 11, 2019
    Inventors: Nusrat ISLAM, Gengbin ZHENG, Sayantan SUR, Maria GARZARAN, Akhil LANGER
  • Publication number: 20190042527
    Abstract: Various embodiments are generally directed to techniques for collective operations among compute nodes in a distributed processing set, such as by utilizing ring sets and local sets of the distributed processing set. In some embodiments, a ring set may include a subset of the distributed processing set in which each compute node is connected to a network with a separate router. In various embodiments, a local set may include a subset of the distributed processing set in which each compute node is connected to a network with a common router. In one or more embodiments, each compute node in a distributed processing set may belong to one ring set and one local set.
    Type: Application
    Filed: December 28, 2017
    Publication date: February 7, 2019
    Inventor: Akhil Langer
  • Publication number: 20190045003
    Abstract: Particular embodiments described herein provide for a device that can be configured to receive data from a first node in a bi-directional chain of nodes, perform a reduction operation that is part of a collective communication operation using the data from the first node and data on the node to create a first intermediate result, store the first intermediate result in memory, communicate the first intermediate result to a second node, receive second data from the second node, perform the reduction operation that is part of the collective communication operation using the second data from the second node and the data on the node to create a second intermediate result, communicate the second intermediate result to the first node, and perform the collective communication operation using the second data from the second node and the first intermediate collective communication operation result to create a collective communication operation result.
    Type: Application
    Filed: January 9, 2018
    Publication date: February 7, 2019
    Applicant: Intel Corporation
    Inventors: Charles Archer, Akhil Langer
  • Publication number: 20180183857
    Abstract: Particular embodiments described herein provide for an electronic device that can be configured to consolidate data from one or more processes on a node, where the node is part of a first collection of nodes, communicate the consolidated data to a second node, where the second node is in the first collection of nodes, where the first collection of nodes is part of a first group of a collection of nodes, and communicate the consolidated data to a third node, wherein the third node is in a second collection of nodes, where the second collection of nodes is part of the first group of the collection of nodes. In an example, the node is part of a multi-tiered dragonfly topology network and the data is part of a gather or scatter process.
    Type: Application
    Filed: December 23, 2016
    Publication date: June 28, 2018
    Applicant: Intel Corporation
    Inventors: Akhil Langer, Sayantan Sur