Abstract: A method includes obtaining a base structure of an electronic device, the base structure including at least one opening, and forming, using a reactive-ion deposition process, a dielectric material within the at least one opening.

Abstract: Exemplary semiconductor structures and processing methods may include forming a first portion of a first semiconductor layer characterized by a first etch rate for an etch treatment, forming a second portion of the first semiconductor layer characterized by a second etch rate that is less than the first etch rate for the etch treatment, and forming a third portion of the first semiconductor layer characterized by a third etch rate that is greater than the second etch rate. The processing methods may further include etching an opening through the first semiconductor layer, where the opening has a height and a width, and where the opening is characterized by a variation in the width between a midpoint of the height of the opening and an endpoint of the opening that is less than or about 5 ?.

Abstract: Exemplary methods of semiconductor processing may include providing deposition precursors to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region. The deposition precursors may include a silicon-containing precursor. The methods may include providing a dopant precursor to the processing region of the semiconductor processing chamber. The dopant precursor may include a phosphorous-containing precursor. The methods may include generating plasma effluents of the deposition precursors and the dopant precursor. The methods may include depositing a silicon-containing material on the substrate. The silicon-containing material may be characterized by a stress of greater than or about ?50 MPa.

Abstract: Embodiments disclosed herein include a semiconductor processing tool. In an embodiment, the semiconductor processing tool comprises a chamber, a pedestal in the chamber, and a first gas feed system on a first side of the pedestal. In an embodiment, the first gas feed system comprises a first exhaust line with a first valve to open and close the first exhaust line, and a first source gas feed line with a second valve to open and close the first source gas feed line. In an embodiment, the semiconductor processing tool further comprises a second gas feed system on a second side of the pedestal. In an embodiment, the second gas feed system comprises a second exhaust line with a third valve to open and close the second exhaust line, and a second source gas feed line with a fourth valve to open and close the second source gas feed line.

Abstract: A plasma processing system is provided. The system includes a hydrogen gas supply and a hydrocarbon gas supply and a processing chamber. The system includes a first mass flow controller (MFC) for controlling hydrogen gas flow into the processing chamber and a second MFC for controlling hydrocarbon gas flow into the processing chamber. The system includes a plasma source for generating plasma at the processing chamber. The plasma is for etching SnO2. The system includes a controller for regulating the first MFC and the second MFC such that a ratio of hydrocarbon gas flow to the hydrogen gas flow into the processing chamber is between 1% and 60% so that when SnH4 is produced during said etching SnO2. The SnH4 is configured to react with hydrocarbon gas to produce an organotin compound that is volatilizable in a reaction that is more kinetically favorable than SnH4 decomposition into Sn powder.

Abstract: An Atomic Layer Deposition (ALD) method to deposit a metal oxide layer onto an organic photoresist on a substrate using a highly reactive organic metal precursor. The deposition method protects the organic photoresist from loss and degradation from exposure to oxygen species during subsequent ALD cycles. The organic metal precursor may be an amino type precursor or a methoxy type precursor.

Abstract: Exemplary semiconductor structures and processing methods may include forming a first portion of a first semiconductor layer characterized by a first etch rate for an etch treatment, forming a second portion of the first semiconductor layer characterized by a second etch rate that is less than the first etch rate for the etch treatment, and forming a third portion of the first semiconductor layer characterized by a third etch rate that is greater than the second etch rate. The processing methods may further include etching an opening through the first semiconductor layer, where the opening has a height and a width, and where the opening is characterized by a variation in the width between a midpoint of the height of the opening and an endpoint of the opening that is less than or about 5 ?.

Abstract: Exemplary semiconductor structures and processing methods may include forming a first portion of a first semiconductor layer characterized by a first etch rate for an etch treatment, forming a second portion of the first semiconductor layer characterized by a second etch rate that is less than the first etch rate for the etch treatment, and forming a third portion of the first semiconductor layer characterized by a third etch rate that is greater than the second etch rate. The processing methods may further include etching an opening through the first semiconductor layer, where the opening has a height and a width, and where the opening is characterized by a variation in the width between a midpoint of the height of the opening and an endpoint of the opening that is less than or about 5 ?.

Abstract: Semiconductor processing systems and method are described that may include flowing deposition precursors into a substrate processing region of a semiconductor processing chamber, where the substrate processing region includes an electrostatic chuck. The methods may further include depositing a seasoning layer on the electrostatic chuck from the deposition precursors to form a seasoned electrostatic chuck. The seasoning layer may be characterized by a dielectric constant greater than or about 3.5. The methods may still further include applying a voltage to the seasoned electrostatic chuck of greater than or about 500 V. The seasoned electrostatic chuck may be characterized by a leakage current of less than or about 25 mA when the voltage is applied.

Abstract: Methods and apparatuses for performing spacer on spacer multiple patterning schemes using an exhumable first spacer material and a complementary second spacer material. Certain embodiments involve using a tin oxide spacer material for one of the spacer materials in spacer on spacer self aligned multiple patterning.

Abstract: Various embodiments herein relate to methods, apparatus, and systems for etching a feature in a substrate. Typically the feature is etched in a dielectric-containing stack. The etching process involves cyclically etching the feature and depositing a protective film on sidewalls of the partially etched feature. These stages are repeated until the feature reaches its final depth. The protective film may have a particular composition, for example including at least one of a tungsten carbonitride, a tungsten sulfide, tin, a tin-containing compound, molybdenum, a molybdenum-containing compound, a ruthenium carbonitride, a ruthenium sulfide, an aluminum carbonitride, an aluminum sulfide, zirconium, and a zirconium-containing compound. A number of optional steps may be taken including, for example, doping the mask layer, pre-treating the substrate prior to deposition, removing the protective film from the sidewalls, and oxidizing any remaining protective film.

Abstract: Semiconductor processing systems and method are described that may include flowing deposition precursors into a substrate processing region of a semiconductor processing chamber, where the substrate processing region includes an electrostatic chuck. The methods may further include depositing a seasoning layer on the electrostatic chuck from the deposition precursors to form a seasoned electrostatic chuck. The seasoning layer may be characterized by a dielectric constant greater than or about 3.5. The methods may still further include applying a voltage to the seasoned electrostatic chuck of greater than or about 500 V. The seasoned electrostatic chuck may be characterized by a leakage current of less than or about 25 mA when the voltage is applied.

Abstract: Methods, apparatus, and systems are provided herein for processing a substrate. Generally, the processing involves Spacer-on-Spacer (SoS) Self-Aligned Quadruple Patterning (SAQP) techniques. The disclosed techniques provide a novel process flow that reduces defects by ensuring that cores are not removed from the substrate until the substrate is transferred to a deposition chamber used to deposit a second spacer layer. This reduces or eliminates the risk of structural damage to features on the substrate while the substrate is being transferred or cleaned. Such structural damage is common when the cores are removed from the substrate prior to cleaning and transfer.

Abstract: Processing methods and apparatus for depositing a protective layer on internal surfaces of a reaction chamber are provided. One method may include depositing, while no wafers are present in the reaction chamber having interior surfaces, a first layer of protective material onto the interior surfaces, the interior surfaces comprising a first material, processing, after the depositing the first layer, a portion of a batch of wafers within a reaction chamber, measuring an amount of the first material in the reaction chamber during processing the portion of the batch of wafers, or on one of the wafers in the portion of the batch of wafers, determining that the first amount exceeds a threshold, and depositing, in response to determining that the first amount exceeds the threshold and while no wafers are present in the reaction chamber, a second layer of protective material onto the interior surfaces of the reaction chamber.

Abstract: Exemplary deposition methods may include delivering a silicon-containing precursor and an inert gas to a processing region of a semiconductor processing chamber. The methods may include providing a hydrogen-containing precursor with the silicon-containing precursor and the inert gas. The methods may include forming a plasma of all precursors within the processing region of a semiconductor processing chamber. The methods may include depositing a silicon-containing material on a substrate disposed within the processing region of the semiconductor processing chamber. The processing region may be maintained free of helium delivery during the deposition method.

Abstract: A method for patterning a substrate includes providing a substrate, and depositing a multi-layer stack including N layers on the substrate. N is an integer greater than one. The N layers include N mean free paths for secondary electrons, respectively. The method includes depositing a photoresist layer on the multi-layer stack, wherein the N mean free paths converge in the photoresist layer. Another method for patterning a substrate includes providing a substrate and depositing a layer on the substrate. The layer includes varying mean free paths for secondary electrons. The method includes depositing a photoresist layer on the layer. The varying mean free paths for secondary electrons converge in the photoresist layer.

Abstract: Exemplary semiconductor structures and processing methods may include forming a first portion of a first semiconductor layer characterized by a first etch rate for an etch treatment, forming a second portion of the first semiconductor layer characterized by a second etch rate that is less than the first etch rate for the etch treatment, and forming a third portion of the first semiconductor layer characterized by a third etch rate that is greater than the second etch rate.

Abstract: Semiconductor processing systems and method are described that may include flowing deposition precursors into a substrate processing region of a semiconductor processing chamber, where the substrate processing region includes an electrostatic chuck. The methods may further include depositing a seasoning layer on the electrostatic chuck from the deposition precursors to form a seasoned electrostatic chuck. The seasoning layer may be characterized by a dielectric constant greater than or about 3.5. The methods may still further include applying a voltage to the seasoned electrostatic chuck of greater than or about 500 V. The seasoned electrostatic chuck may be characterized by a leakage current of less than or about 25 mA when the voltage is applied.

Abstract: An in situ protective coating is deposited on surfaces of chamber components of a reaction chamber at high temperatures. The in situ protective coating may be deposited at a temperature greater than about 200° C. to provide a high quality coating that is resistant to certain types of halogen chemistries, such as fluorine-based species, chlorine-based species, bromine-based species, or iodine-based species. Subsequent coatings or layers may be deposited on the in situ protective coating having different etch selectivities than the underlying in situ protective coating. The in situ protective coating may be deposited throughout the reaction chamber to deposit on surfaces of the chamber components, including on chamber walls.

Abstract: Various embodiments herein relate to methods, apparatus, and systems for etching a feature in a substrate. Typically the feature is etched in a dielectric-containing stack. The etching process involves cyclically etching the feature and depositing a protective film on sidewalls of the partially etched feature. These stages are repeated until the feature reaches its final depth. The protective film may have a particular composition, for example including at least one of a tungsten carbonitride, a tungsten sulfide, tin, a tin-containing compound, molybdenum, a molybdenum-containing compound, a ruthenium carbonitride, a ruthenium sulfide, an aluminum carbonitride, an aluminum sulfide, zirconium, and a zirconium-containing compound. A number of optional steps may be taken including, for example, doping the mask layer, pre-treating the substrate prior to deposition, removing the protective film from the sidewalls, and oxidizing any remaining protective film.