Patents by Inventor Akhila Mallavarapu
Akhila Mallavarapu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240124726Abstract: Provided are nanostructure imprinting processes that utilize dispersions of nanoparticles in aqueous solvents. Also provided are nanostructure imprinting processes that utilize temperature-sensitive solvents that can be thinned via application of temperature. Such solvents allow for formation of nanostructures of particular height.Type: ApplicationFiled: October 10, 2023Publication date: April 18, 2024Inventors: Akhila Mallavarapu, Chavez FK Lawrence, Cherie R. Kagan
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Patent number: 11881435Abstract: A method for fabricating a three-dimensional (3D) static random-access memory (SRAM) architecture using catalyst influenced chemical etching (CICE). Utilizing CICE, semiconductor fins can be etched with no etch taper, smooth sidewalls and no maximum height limitation. CICE enables stacking of as many nanosheet layers a desired and also enables a 3D stacked architecture for SRAM cells. Furthermore, CICE can be used to etch silicon waveguides thereby creating waveguides with smooth sidewalls to improve transmission efficiency and, for photon-based quantum circuits, to eliminate charge fluctuations that may affect photon indistinguishability.Type: GrantFiled: May 3, 2022Date of Patent: January 23, 2024Assignee: Board of Regents, The University of Texas SystemInventors: Sidlgata V. Sreenivasan, Akhila Mallavarapu, Jaydeep Kulkarni, Michael Watts, Sanjay Banerjee
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Publication number: 20230411178Abstract: A method and system for etching a semiconductor substrate using catalyst influenced chemical etching. A group of independently controlled discrete actuators are configured to control a depth of an etch of a material on a substrate, where at least two of the group of independently controlled discrete actuators has distinct actuation values. Furthermore, the etch depth has a variation of less than 10% of a feature height across the substrate.Type: ApplicationFiled: October 29, 2021Publication date: December 21, 2023Inventors: Sidlgata V. Sreenivasan, Akhila Mallavarapu, Paras Ajay
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Publication number: 20230285966Abstract: A diagnostic chip for detecting biomarkers and trace amounts of nanoparticles in chemical mixtures or in water. The diagnostic chip includes one or more inputs, where a sample containing differently sized particles is introduced into at least one of these inputs. Furthermore, the diagnostic chip includes multiple separation regions, where the sample is pressurized as it passes through the separation regions. Each separation region includes a deterministic lateral displacement array, where the deterministic lateral displacement array in two or more of these separation regions has a different etch depth profile. In this manner, the diagnostic chip effectively detects biomarkers and trace amounts of nanoparticles in chemical mixtures or in water.Type: ApplicationFiled: July 29, 2021Publication date: September 14, 2023Inventors: Sidlgata V. Sreenivasan, Aryan Mehboudi, Akhila Mallavarapu, Paras Ajay, Raul Marcel Lema Galindo, Mark Hrdy
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Publication number: 20230245996Abstract: A method for bonding with precision alignment. A first bonding surface is bonded with a second bonding surface, where features on the first and second bonding surfaces are precisely overlaid during the bonding. An etch is then performed on the first and/or second bonding surfaces to create recesses in the first and/or second bonding surfaces. Precision alignment of the first and second bonding surfaces is then enabled by a volatile fluid deployed between the first and second bonding surfaces, where the recesses enable removal of the volatile fluid from a bonding interface during and after the bonding.Type: ApplicationFiled: April 7, 2023Publication date: August 3, 2023Inventors: Sidlgata V. Sreenivasan, Paras Ajay, Akhila Mallavarapu, Crystal Barrera
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Publication number: 20230230954Abstract: A system for assembling fields from a source substrate onto a second substrate. The source substrate includes fields. The system further includes a transfer chuck that is used to pick at least four of the fields from the source substrate in parallel to be transferred to the second substrate, where the relative positions of the at least four of the fields is predetermined.Type: ApplicationFiled: March 28, 2022Publication date: July 20, 2023Inventors: Sidlgata V. Sreenivasan, Paras Ajay, Akhila Mallavarapu, Crystal Barrera
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Publication number: 20230187213Abstract: A method for fabricating silicon nanostructures. An etch uniformity improving layer is deposited on a substrate. A catalyst (e.g., thin film of Ti/Au) is deposited on the substrate or the etch uniformity improving layer, where the catalyst is contacting a portion of the substrate or the etch uniformity layer. The catalyst and the substrate or etch uniformity improving layer are exposed to an etchant, where the catalyst causes etching of the substrate thereby creating etched nanostructures.Type: ApplicationFiled: May 5, 2021Publication date: June 15, 2023Inventors: Sidlgata V. Sreenivasan, Akhila Mallavarapu, Paras Ajay, Mariana Castaneda, Crystal Barrera
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Publication number: 20220270930Abstract: A method for fabricating a three-dimensional (3D) static random-access memory (SRAM) architecture using catalyst influenced chemical etching (CICE). Utilizing CICE, semiconductor fins can be etched with no etch taper, smooth sidewalls and no maximum height limitation. CICE enables stacking of as many nanosheet layers a desired and also enables a 3D stacked architecture for SRAM cells. Furthermore, CICE can be used to etch silicon waveguides thereby creating waveguides with smooth sidewalls to improve transmission efficiency and, for photon-based quantum circuits, to eliminate charge fluctuations that may affect photon indistinguishability.Type: ApplicationFiled: May 3, 2022Publication date: August 25, 2022Inventors: Sidlgata V. Sreenivasan, Akhila Mallavarapu, Jaydeep Kulkarni, Michael Watts, Sanjay Banerjee
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Patent number: 11355397Abstract: A method for fabricating a three-dimensional (3D) static random-access memory (SRAM) architecture using catalyst influenced chemical etching (CICE). Utilizing CICE, semiconductor fins can be etched with no etch taper, smooth sidewalls and no maximum height limitation. CICE enables stacking of as many nanosheet layers a desired and also enables a 3D stacked architecture for SRAM cells. Furthermore, CICE can be used to etch silicon waveguides thereby creating waveguides with smooth sidewalls to improve transmission efficiency and, for photon-based quantum circuits, to eliminate charge fluctuations that may affect photon indistinguishability.Type: GrantFiled: May 12, 2020Date of Patent: June 7, 2022Assignee: Board of Regents, The University of Texas SystemInventors: Sidlgata V. Sreenivasan, Akhila Mallavarapu, Jaydeep Kulkarni, Michael Watts, Sanjay Banerjee
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Publication number: 20220139717Abstract: Various embodiments of the present technology generally relate to semiconductor device architectures and manufacturing techniques. More specifically, some embodiments of the present technology relate to large area metrology and process control for anisotropic chemical etching. Catalyst influenced chemical etching (CICE) can be used to create high aspect ratio semiconductor structures with dimensions in the nanometer to millimeter scale with anisotropic and smooth sidewalls. However, all aspects of the CICE process must be compatible with the equipment used in semiconductor fabrication facilities today, and they must be scalable to enable wafer scale processing with high yield and reliability. This invention relates to metrology and control of etch and CMOS compatible methods of patterning the catalyst and removing it without damaging the etched structures.Type: ApplicationFiled: February 24, 2020Publication date: May 5, 2022Inventors: Sidlgata V. Sreenivasan, Akhila Mallavarapu, John G. Ekerdt, Michelle A. Grigas, Ziam Ghaznavi, Paras Ajay
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Publication number: 20200365464Abstract: A method for fabricating a three-dimensional (3D) static random-access memory (SRAM) architecture using catalyst influenced chemical etching (CICE). Utilizing CICE, semiconductor fins can be etched with no etch taper, smooth sidewalls and no maximum height limitation. CICE enables stacking of as many nanosheet layers a desired and also enables a 3D stacked architecture for SRAM cells. Furthermore, CICE can be used to etch silicon waveguides thereby creating waveguides with smooth sidewalls to improve transmission efficiency and, for photon-based quantum circuits, to eliminate charge fluctuations that may affect photon indistinguishability.Type: ApplicationFiled: May 12, 2020Publication date: November 19, 2020Inventors: Sidlgata V. Sreenivasan, Akhila Mallavarapu, Jaydeep Kulkarni, Michael Watts, Sanjay Banerjee
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Patent number: 10026609Abstract: A method for template fabrication of ultra-precise nanoscale shapes. Structures with a smooth shape (e.g., circular cross-section pillars) are formed on a substrate using electron beam lithography. The structures are subject to an atomic layer deposition of a dielectric interleaved with a deposition of a conductive film leading to nanoscale sharp shapes with features that exceed electron beam resolution capability of sub-10 nm resolution. A resist imprint of the nanoscale sharp shapes is performed using J-FIL. The nanoscale sharp shapes are etched into underlying functional films on the substrate forming a nansohaped template with nanoscale sharp shapes that include sharp corners and/or ultra-small gaps. In this manner, sharp shapes can be retained at the nanoscale level. Furthermore, in this manner, imprint based shape control for novel shapes beyond elementary nanoscale structures, such as dots and lines, can occur at the nanoscale level.Type: GrantFiled: October 23, 2015Date of Patent: July 17, 2018Assignee: Board of Regents, The University of Texas SystemInventors: Sidlgata V. Sreenivasan, Anshuman Cherala, Meghali Chopra, Roger Bonnecaze, Ovadia Abed, Bailey Yin, Akhila Mallavarapu, Shrawan Singhal, Brian Gawlik
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Patent number: 9972699Abstract: Methods for fabricating and replicating self-aligned multi-tier nanoscale structures for a variety of cross-sectional geometries. These methods can utilize a single lithography step whereby the need for alignment and overlay in the process is completely eliminated thereby enabling near-zero overlay error. Furthermore, techniques are developed to use these methods to fabricate self-aligned nanoscale multi-level/multi-height patterns with various shapes for master templates, replica templates and nanoimprint based pattern replication. Furthermore, the templates can be used to pattern multiple levels in a sacrificial polymer resist and achieve pattern transfer of the levels into a variety of substrates to form completed large area nanoelectronic and nanophotonic devices using only one patterning step.Type: GrantFiled: February 26, 2018Date of Patent: May 15, 2018Assignee: Board of Regents, The University of Texas SystemInventors: Sidlgata V. Sreenivasan, Praveen Joseph, Ovadia Abed, Michelle Grigas, Akhila Mallavarapu, Paras Ajay
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Patent number: 9972698Abstract: Methods for fabricating and replicating self-aligned multi-tier nanoscale structures for a variety of cross-sectional geometries. These methods can utilize a single lithography step whereby the need for alignment and overlay in the process is completely eliminated thereby enabling near-zero overlay error. Furthermore, techniques are developed to use these methods to fabricate self-aligned nanoscale multi-level/multi-height patterns with various shapes for master templates, replica templates and nanoimprint based pattern replication. Furthermore, the templates can be used to pattern multiple levels in a sacrificial polymer resist and achieve pattern transfer of the levels into a variety of substrates to form completed large area nanoelectronic and nanophotonic devices using only one patterning step.Type: GrantFiled: February 26, 2018Date of Patent: May 15, 2018Assignee: Board of Regents, The University of Texas SystemInventors: Sidlgata V. Sreenivasan, Praveen Joseph, Ovadia Abed, Michelle Grigas, Akhila Mallavarapu, Paras Ajay
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Patent number: 9941389Abstract: Methods for fabricating and replicating self-aligned multi-tier nanoscale structures for a variety of cross-sectional geometries. These methods can utilize a single lithography step whereby the need for alignment and overlay in the process is completely eliminated thereby enabling near-zero overlay error. Furthermore, techniques are developed to use these methods to fabricate self-aligned nanoscale multi-level/multi-height patterns with various shapes for master templates, replica templates and nanoimprint based pattern replication. Furthermore, the templates can be used to pattern multiple levels in a sacrificial polymer resist and achieve pattern transfer of the levels into a variety of substrates to form completed large area nanoelectronic and nanophotonic devices using only one patterning step.Type: GrantFiled: April 19, 2016Date of Patent: April 10, 2018Assignee: Board of Regents, The University of Texas SystemInventors: Sidlgata V. Sreenivasan, Praveen Joseph, Ovadia Abed, Michelle Grigas, Akhila Mallavarapu, Paras Ajay
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Publication number: 20160308020Abstract: Methods for fabricating and replicating self-aligned multi-tier nanoscale structures for a variety of cross-sectional geometries. These methods can utilize a single lithography step whereby the need for alignment and overlay in the process is completely eliminated thereby enabling near-zero overlay error. Furthermore, techniques are developed to use these methods to fabricate self-aligned nanoscale multi-level/multi-height patterns with various shapes for master templates, replica templates and nanoimprint based pattern replication. Furthermore, the templates can be used to pattern multiple levels in a sacrificial polymer resist and achieve pattern transfer of the levels into a variety of substrates to form completed large area nanoelectronic and nanophotonic devices using only one patterning step.Type: ApplicationFiled: April 19, 2016Publication date: October 20, 2016Inventors: Sidlgata V. Sreenivasan, Praveen Joseph, Ovadia Abed, Michelle Grigas, Akhila Mallavarapu, Paras Ajay
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Publication number: 20160118249Abstract: A method for template fabrication of ultra-precise nanoscale shapes. Structures with a smooth shape (e.g., circular cross-section pillars) are formed on a substrate using electron beam lithography. The structures are subject to an atomic layer deposition of a dielectric interleaved with a deposition of a conductive film leading to nanoscale sharp shapes with features that exceed electron beam resolution capability of sub-10 nm resolution. A resist imprint of the nanoscale sharp shapes is performed using J-FIL. The nanoscale sharp shapes are etched into underlying functional films on the substrate forming a nansohaped template with nanoscale sharp shapes that include sharp corners and/or ultra-small gaps. In this manner, sharp shapes can be retained at the nanoscale level. Furthermore, in this manner, imprint based shape control for novel shapes beyond elementary nanoscale structures, such as dots and lines, can occur at the nanoscale level.Type: ApplicationFiled: October 23, 2015Publication date: April 28, 2016Inventors: Sidlgata V. Sreenivasan, Anshuman Cherala, Meghali Chopra, Roger Bonnecaze, Ovadia Abed, Bailey Yin, Akhila Mallavarapu, Shrawan Singhal, Brian Gawlik