Abstract: A retorted gluten-free pasta product that survives retort may be formed by preparing a dry mix that includes (a) a gluten-free flour that includes (i) a non-cereal flour or pulse flour, (ii) a cereal flour, or (iii) mixtures thereof, (b) a starch, and (c) an emulsifier. The dry mix may be combined with water to form a dough that can be extruded at a temperature and with an amount of mechanical energy effective to form an extruded pasta product having a bi-continuous matrix of protein and starch. The pasta product can be incorporated with a sauce into a closed retort container and subsequently retorted. The resulting retorted food product may contain gluten-free pasta that has the structural integrity and textual firmness consistent with that exhibited by traditional wheat pasta after having undergone retort.

Abstract: At least one method, apparatus and system disclosed involves hard-coding data into an integrated circuit device. An integrated circuit device provided. Data for hard-wiring information into a portion of the integrated circuit device is received. A stress voltage signal is provided to a portion of a transistor of the integrated circuit device for causing a dielectric breakdown of the portion of the transistor for hard-wiring the data.

Abstract: We disclose methods, apparatus, and systems for improving semiconductor device writeability through bias temperature instability. Such a device may comprise a plurality of cells of an array, wherein each of the cells comprises a pass gate and a latch; a plurality of word lines, wherein each word line comprises a supply voltage line (VCS) which supplies voltage to each latch of a first number of cells; an array VCS driver electrically connected to each VCS; and a control line configured to provide an operational array supply voltage, a first array supply voltage, or a second array supply voltage to each VCS through the array VCS driver.

Abstract: At least one method, apparatus and system disclosed involves hard-coding data into an integrated circuit device. An integrated circuit device provided. Data for hard-wiring information into a portion of the integrated circuit device is received. A stress voltage signal is provided to a portion of a transistor of the integrated circuit device for causing a dielectric breakdown of the portion of the transistor for hard-wiring the data.

Abstract: Method, apparatus, and system for improving semiconductor device writeability at row/bit level through bias temperature instability. Such a device may comprise a plurality of cells of an array, wherein each of the cells comprises a pass gate and a latch; a plurality of word lines, wherein each word line comprises a supply voltage line (VCS) which supplies voltage to each latch of a first number of cells; an array VCS driver electrically connected to each VCS; and a control line configured to provide an operational array supply voltage, a first array supply voltage, or a second array supply voltage to each VCS, wherein the first array supply voltage and the second array supply voltage are greater than the operational array supply voltage. By virtue of BTI, application of the first array supply voltage may lead to improved writeability of one or more cells of the device.

Abstract: At least one method, apparatus and system disclosed involves hard-coding data into an integrated circuit device. An integrated circuit device provided. Data for hard-wiring information into a portion of the integrated circuit device is received. A stress voltage signal is provided to a portion of a transistor of the integrated circuit device for causing a dielectric breakdown of the portion of the transistor for hard-wiring the data.

Abstract: We disclose methods, apparatus, and systems for improving semiconductor device writeability through bias temperature instability. Such a device may comprise a plurality of cells of an array, wherein each of the cells comprises a pass gate and a latch; a plurality of word lines, wherein each word line comprises a supply voltage line (VCS) which supplies voltage to each latch of a first number of cells; an array VCS driver electrically connected to each VCS; and a control line configured to provide an operational array supply voltage, a first array supply voltage, or a second array supply voltage to each VCS through the array VCS driver.

Abstract: Method, apparatus, and system for improving semiconductor device writeability at row/bit level through bias temperature instability. Such a device may comprise a plurality of cells of an array, wherein each of the cells comprises a pass gate and a latch; a plurality of word lines, wherein each word line comprises a supply voltage line (VCS) which supplies voltage to each latch of a first number of cells; an array VCS driver electrically connected to each VCS; and a control line configured to provide an operational array supply voltage, a first array supply voltage, or a second array supply voltage to each VCS, wherein the first array supply voltage and the second array supply voltage are greater than the operational array supply voltage. By virtue of BTI, application of the first array supply voltage may lead to improved writeability of one or more cells of the device.

Abstract: We disclose methods, apparatus, and systems for improving semiconductor device writeability through bias temperature instability. Such a device may comprise a plurality of cells of an array, wherein each of the cells comprises a pass gate and a latch; a plurality of word lines, wherein each word line comprises a supply voltage line (VCS) which supplies voltage to each latch of a first number of cells; an array VCS driver electrically connected to each VCS; and a control line configured to provide an operational array supply voltage, a first array supply voltage, or a second array supply voltage to each VCS through the array VCS driver.

Abstract: We disclose methods, apparatus, and systems for improving semiconductor device yield and/or reliability through bias temperature instability (BTI). One device may comprise a plurality of cells of an array, wherein each of the cells comprises a pass gate and a latch; a plurality of word lines, wherein each word line controls access to each pass gate of a first number of cells; a word line driver electrically connected to each word line; a row decoder configured to authorize or deauthorize a write voltage to each word line through the word line driver, wherein the write voltage is selected from an operational write voltage or a first write voltage; and a control line configured to provide an operational write voltage or a first write voltage to each word line authorized by the row decoder, wherein the first write voltage is greater than an operational write voltage.

Abstract: We disclose methods, apparatus, and systems for improving semiconductor device yield and/or reliability through bias temperature instability (BTI). One device may comprise a plurality of cells of an array, wherein each of the cells comprises a pass gate and a latch; a plurality of word lines, wherein each word line controls access to each pass gate of a first number of cells; a word line driver electrically connected to each word line; and a control line configured to provide an operational write voltage or a first write voltage to each word line through the word line driver. By virtue of BTI, application of the first write voltage may lead to improved stability of data desired to be read from one or more cells of the device.

Abstract: A method of forming an OTPROM capable of storing twice the number of bits as a conventional OTPROM without increasing the overall size of the device is provided. Embodiments include forming a OTPROM, the OTPROM array having a plurality of formed devices; receiving a binary code to program the OTPROM array; separating the binary code into a first part and a second part; programming each device with one of four data storage states by: forming a gate oxide layer of each device to a thickness corresponding to the first part of the binary code, and selectively applying a TDDB stress to the gate oxide layer corresponding to the second part of the binary code; detecting a Idsat level discharged by each device with a multi-bit sense amplifier; and reading the state of each device based on the detected Idsat level.

Abstract: A method of forming an OTPROM capable of storing twice the number of bits as a conventional OTPROM without increasing the overall size of the device is provided. Embodiments include forming a OTPROM, the OTPROM array having a plurality of formed devices; receiving a binary code to program the OTPROM array; separating the binary code into a first part and a second part; programming each device with one of four data storage states by: forming a gate oxide layer of each device to a thickness corresponding to the first part of the binary code, and selectively applying a TDDB stress to the gate oxide layer corresponding to the second part of the binary code; detecting a Idsat level discharged by each device with a multi-bit sense amplifier; and reading the state of each device based on the detected Idsat level.

Abstract: At least one method, apparatus and system disclosed involves hard-coding data into an integrated circuit device. An integrated circuit device provided. Data for hard-wiring information into a portion of the integrated circuit device is received. A stress voltage signal is provided to a portion of a transistor of the integrated circuit device for causing a dielectric breakdown of the portion of the transistor for hard-wiring the data.

Abstract: A sensing device for a data storage system may include a sensing circuit, a pull-down circuit, and a pull-up circuit. The sensing circuit may sense discharging of a desired bit line or a complementary bit line and may generate a desired output. The pull-down circuit may be coupled to the bit line and the complementary bit line for enhancing the discharging rate and may increase the sensing speed of the storage system. The pull-up circuit may control the discharging of an undesired bit line or complementary bit line.

Abstract: An extruded legume snack food comprising an extruded puff product based on a dried legume powder having a shape that is a facsimile of the natural starting material, such as a pea pod. A legume powder is mixed with a starch, extruded, and then shaped. The extrudate can be shaped by a number of forming devices or, in an alternative embodiment, by the orifice shape of an extrusion die when the extrudate is face cut from the extruder.

Abstract: A nutrition bar which incorporates protein in the form of nuggets having high levels of selected proteins. By use of the nuggets of the invention, nutrition bars are formulated to have elevated levels of protein, yet good taste and other organoleptic properties. The nuggets according to the invention include greater than 50 wt % of a non-soy protein selected from the group consisting of milk protein, rice protein and pea protein, especially between 51 wt % and 99 wt %, more preferably between 52 wt % and 95 wt %, most preferably 55 wt % or above. The milk protein is preferably whey protein. The nuggets of the invention are preferably made using an extrusion process wherein the extrusion temperature is moderated so as to avoid damage to the whey proteins and concomitant off-taste. In this preferred process according to the invention, extrusion is conducted at temperatures of from 60 to 140° C., after which the protein is dried using a belt/conveyor drier or a fluid bed drier.

Abstract: Food bars, especially low carbohydrate layered food bars, having good organoleptic properties prepared using mesomorphic phase of edible surfactant in the crème or filling layer. Preferably, the mesophase is present in the filling layer in bulk. By use of mesophase surfactants, it is possible to minimize or eliminate sugar alcohols from common crème layers such as caramel and marshmallow and still produce a bar of similar or larger size with lower or comparable caloric impact to the sugar alcohol-containing bars. Preferably, the mesophase has a water activity of less than 0.7 and a water content of less than 80%, especially 75% or less. Preferably, the mesophase includes at least 5 wt % surfactants, especially at least 15 wt. % surfactants, preferably mono- and di-glycerides. A preferred range for the mono- and diglycerides is from 15 to 20 wt. %.

Abstract: A nutrition bar which incorporates protein in the form of nuggets having high levels of selected proteins. By use of the nuggets of the invention, nutrition bars are formulated to have elevated levels of protein, yet good taste and other organoleptic properties. The nuggets according to the invention include greater than 50 wt % of a non-soy protein selected from the group consisting of milk protein, rice protein and pea protein, especially between 51 wt % and 99 wt %, more preferably between 52 wt % and 95 wt %, most preferably 55 wt % or above. The milk protein is preferably whey protein. The nuggets of the invention are preferably made using an extrusion process wherein the extrusion temperature is moderated so as to avoid damage to the whey proteins and concomitant off-taste. In this preferred process according to the invention, extrusion is conducted at temperatures of from 60 to 140° C., after which the protein is dried using a belt/conveyor drier or a fluid bed drier.

Abstract: A nutrition or other food bar which includes, preferably in moderate to high levels, peptides in the form of hydrated high water activity peptides. The peptides are typically either intact proteins or hydrolyzed proteins. Inclusion of peptides in the form of high water activity peptides helps prevent migration of water from sugars to the proteins which would otherwise result in formation of hard crystalline sugars and food bars which are excessively hard. Whey protein isolate and hydrolyzed whey protein are preferred high water activity peptides.