Patents by Inventor Akhilesh Jaiswal
Akhilesh Jaiswal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240021231Abstract: An ultrafast non-volatile memory cell for wafer-scale integration includes a voltage divider that outputs an output voltage. The voltage divider includes a reference resistive device that is a reference magnetic tunnel junction or another reference resistive component and a switchable magnetic tunnel junction that includes a free magnet and a fixed magnet. The switchable magnetic tunnel junction configured such that the free magnet is light switchable between a high impedance state and a low impedance state upon application of an electric signal and incident light. A transistor switch is configured to activate the voltage divider for memory write and read operations. A light modulator is in electrical communication with the output voltage from the voltage divider. The light modulator is configured to modulate a guided light beam for memory read operations. Arrays of the memory cells are also provided.Type: ApplicationFiled: October 5, 2021Publication date: January 18, 2024Applicant: UNIVERSITY OF SOUTHERN CALIFORNIAInventors: Ajey JACOB, Akhilesh JAISWAL
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Publication number: 20230314717Abstract: Provided is an electro-optic transducer comprising: a first optical disk resonator and a second optical disk resonator, wherein the first optical disk resonator and the second optical disk resonator are optically coupled; a waveguide, the waveguide optically coupled to at least one of the first optical disk resonator and the second optical disk resonator; and a resonator, the resonator functionally coupled to at least a portion of the first optical disk resonator and the second optical disk resonator..Type: ApplicationFiled: December 1, 2022Publication date: October 5, 2023Inventors: Ramesh Kudalippalliyalil, Sujith Chandran, Akhilesh Jaiswal, Ajey P. Jacob
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Publication number: 20230305804Abstract: An in-memory vector addition method for a dynamic random access memory (DRAM) is disclosed which includes consecutively transposing two numbers across a plurality of rows of the DRAM, each number transposed across a fixed number of rows associated with a corresponding number of bits, assigning a scratch-pad including two consecutive bits for each bit of each number being added, two consecutive bits for carry-in (Cin), and two consecutive bits for carry-out-bar (Cout), assigning a plurality of bits in a transposed orientation to hold results as a sum of the two numbers, for each bit position of the two numbers: computing the associated sum of the bit position; and placing the computed sum in the associated bit of the sum.Type: ApplicationFiled: June 3, 2023Publication date: September 28, 2023Applicant: Purdue Research FoundationInventors: Mustafa Ali, Akhilesh Jaiswal, Kaushik Roy
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Publication number: 20230176111Abstract: A sensing circuit for detecting hardware trojans in a target integrated circuit is provided. The sensing circuit includes an array of magnetic tunnel junction circuits where each magnetic tunnel junction circuit including one or more magnetic tunnel junctions. Characteristically, each magnetic tunnel junction circuit configured to provide data for and/or determine a temperature map or a current map of the target integrated circuit.Type: ApplicationFiled: April 29, 2021Publication date: June 8, 2023Applicant: UNIVERSITY OF SOUTHERN CALIFORNIAInventors: Ajey JACOB, Akhilesh JAISWAL
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Patent number: 11669302Abstract: An in-memory vector addition method for a dynamic random access memory (DRAM) is disclosed which includes consecutively transposing two numbers across a plurality of rows of the DRAM, each number transposed across a fixed number of rows associated with a corresponding number of bits, assigning a scratch-pad including two consecutive bits for each bit of each number being added, two consecutive bits for carry-in (Cin), and two consecutive bits for carry-out-bar (Cout), assigning a plurality of bits in a transposed orientation to hold results as a sum of the two numbers, for each bit position of the two numbers: computing the associated sum of the bit position; and placing the computed sum in the associated bit of the sum.Type: GrantFiled: October 15, 2020Date of Patent: June 6, 2023Assignee: Purdue Research FoundationInventors: Mustafa Ali, Akhilesh Jaiswal, Kaushik Roy
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Patent number: 11468146Abstract: Disclosed are embodiments of an integrated circuit structure (e.g., a processing chip), which includes an array of integrated pixel and memory cells configured for deep in-sensor, in-memory computing (e.g., of neural networks). Each cell incorporates a memory structure (e.g., DRAM structure or a ROM structure) with a storage node, which stores a first data value (e.g., a binary weight value), and a sensor connected to a sense node, which outputs a second data value (e.g., an analog input value). Each cell is selectively operable in a functional computing mode during which the voltage level on a bit line is adjusted as a function of both the first data value and the second data value. Each cell is further selectively operable in a storage node read mode. Furthermore, depending upon the type of memory structure (e.g., a DRAM structure), each cell is selectively operable in a storage node write mode.Type: GrantFiled: December 6, 2019Date of Patent: October 11, 2022Assignee: GlobalFoundries U.S. Inc.Inventors: Akhilesh Jaiswal, Ajey Poovannummoottil Jacob
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Patent number: 11195580Abstract: Disclosed is a cell that integrates a pixel and a two-terminal non-volatile memory device. The cell can be selectively operated in write, read and functional computing modes. In the write mode, a first data value is stored the memory device. In the read mode, it is read from the memory device. In the functional computing mode, the pixel captures a second data value and a sensed change in an electrical parameter (e.g., voltage or current) on a bitline connected to the cell is a function of both the first and second data value. Also disclosed is an IC structure that includes an array of the cells and, when multiple cells in a given column are concurrently operated in the functional computing mode, the sensed total change in the electrical parameter on the bitline for the column is indicative of a result of a dot product computation.Type: GrantFiled: February 26, 2020Date of Patent: December 7, 2021Assignee: GLOBALFOUNDRIES U.S. Inc.Inventors: Akhilesh Jaiswal, Ajey Poovannummoottil Jacob
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ML-ENABLED ASSURED MICROELECTRONICS MANUFACTURING: A TECHNIQUE TO MITIGATE HARDWARE TROJAN DETECTION
Publication number: 20210342991Abstract: A method for assuring that integrated circuits are free of malicious circuit insertions and/or IC design modifications through mask swapping/addition is provided. The method includes a step of comparing 3D tomographic images constructed from design GDS to the 3D tomographic images constructed from in-line fab metrology data.Type: ApplicationFiled: April 29, 2021Publication date: November 4, 2021Inventors: Ajey Poovannummoottil JACOB, John DAMOULAKIS, Akhilesh JAISWAL, Devanand Krishna SHENOY, Andrew RITTENBACH -
Patent number: 11120857Abstract: Disclosed is a reference circuit having an even number m of groups of m parallel-connected magnetic tunnel junctions (MTJs). The MTJs in half of the groups are programmed to have parallel resistances (RP) and the MTJs in the other half are programmed to have anti-parallel resistances (RAP). Switches connect the groups in series, creating a series-parallel resistor network. The total resistance (RT) of the network has low variability and is essentially equal to half the sum of a nominal RP plus a nominal RAP and can be employed as a reference resistance (RREF). Under specific biasing conditions the series-parallel resistor network can generate a low variability reference parameter (XREF) that is dependent on this RREF. Also disclosed are an integrated circuit (IC) that includes the reference circuit and a magnetic random access memory (MRAM) structure, which uses XREF to determine stored data values in MRAM cells and associated methods.Type: GrantFiled: December 19, 2019Date of Patent: September 14, 2021Assignee: GLOBALFOUNDRIES U.S. Inc.Inventors: Akhilesh Jaiswal, Bipul C. Paul
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Publication number: 20210264973Abstract: Disclosed is a cell that integrates a pixel and a two-terminal non-volatile memory device. The cell can be selectively operated in write, read and functional computing modes. In the write mode, a first data value is stored the memory device. In the read mode, it is read from the memory device. In the functional computing mode, the pixel captures a second data value and a sensed change in an electrical parameter (e.g., voltage or current) on a bitline connected to the cell is a function of both the first and second data value. Also disclosed is an IC structure that includes an array of the cells and, when multiple cells in a given column are concurrently operated in the functional computing mode, the sensed total change in the electrical parameter on the bitline for the column is indicative of a result of a dot product computation.Type: ApplicationFiled: February 26, 2020Publication date: August 26, 2021Applicant: GLOBALFOUNDRIES U.S. Inc.Inventors: Akhilesh Jaiswal, Ajey Poovannummoottil Jacob
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Patent number: 11069402Abstract: Disclosed is a cell that integrates a pixel and a three-terminal non-volatile memory device. The cell can be selectively operated in write, read and functional computing modes. In the write mode, a first data value is stored in the memory device. In the read mode, it is read from the memory device. In the functional computing mode, the pixel captures a second data value and a sensed change in an electrical parameter (e.g., voltage or current) on a bitline connected to the cell is a function of both the first and second data value. Also disclosed is an IC structure that includes an array of the cells and, when multiple cells in a given column are concurrently operated in the functional computing mode, the sensed total change in the electrical parameter on the bitline for the column is indicative of a result of a dot product computation.Type: GrantFiled: March 17, 2020Date of Patent: July 20, 2021Assignee: GLOBALFOUNDRIES U.S. Inc.Inventors: Akhilesh Jaiswal, Ajey Poovannummoottil Jacob
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Publication number: 20210193204Abstract: Disclosed is a reference circuit having an even number m of groups of m parallel-connected magnetic tunnel junctions (MTJs). The MTJs in half of the groups are programmed to have parallel resistances (RP) and the MTJs in the other half are programmed to have anti-parallel resistances (RAP). Switches connect the groups in series, creating a series-parallel resistor network. The total resistance (RT) of the network has low variability and is essentially equal to half the sum of a nominal RP plus a nominal RAP and can be employed as a reference resistance (RREF). Under specific biasing conditions the series-parallel resistor network can generate a low variability reference parameter (XREF) that is dependent on this RREF. Also disclosed are an integrated circuit (IC) that includes the reference circuit and a magnetic random access memory (MRAM) structure, which uses XREF to determine stored data values in MRAM cells and associated methods.Type: ApplicationFiled: December 19, 2019Publication date: June 24, 2021Applicant: GLOBALFOUNDRIES Inc.Inventors: Akhilesh Jaiswal, Bipul C. Paul
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Publication number: 20210173894Abstract: Disclosed are embodiments of an integrated circuit structure (e.g., a processing chip), which includes an array of integrated pixel and memory cells configured for deep in-sensor, in-memory computing (e.g., of neural networks). Each cell incorporates a memory structure (e.g., DRAM structure or a ROM structure) with a storage node, which stores a first data value (e.g., a binary weight value), and a sensor connected to a sense node, which outputs a second data value (e.g., an analog input value). Each cell is selectively operable in a functional computing mode during which the voltage level on a bit line is adjusted as a function of both the first data value and the second data value. Each cell is further selectively operable in a storage node read mode. Furthermore, depending upon the type of memory structure (e.g., a DRAM structure), each cell is selectively operable in a storage node write mode.Type: ApplicationFiled: December 6, 2019Publication date: June 10, 2021Applicant: GLOBALFOUNDRIES U.S. Inc.Inventors: Akhilesh Jaiswal, Ajey Poovannummoottil Jacob
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Publication number: 20210117156Abstract: An in-memory vector addition method for a dynamic random access memory (DRAM) is disclosed which includes consecutively transposing two numbers across a plurality of rows of the DRAM, each number transposed across a fixed number of rows associated with a corresponding number of bits, assigning a scratch-pad including two consecutive bits for each bit of each number being added, two consecutive bits for carry-in (Cin), and two consecutive bits for carry-out-bar (Cout), assigning a plurality of bits in a transposed orientation to hold results as a sum of the two numbers, for each bit position of the two numbers: computing the associated sum of the bit position; and placing the computed sum in the associated bit of the sum.Type: ApplicationFiled: October 15, 2020Publication date: April 22, 2021Applicant: Purdue Research FoundationInventors: Mustafa Ali, Akhilesh Jaiswal, Kaushik Roy
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Patent number: 10964367Abstract: One illustrative MRAM device disclosed herein includes a first bit cell and a second bit cell. The first bit cell comprises a first access transistor and a first MTJ stack. The first MTJ stack comprises a first pinned layer and a first free layer, wherein the first pinned layer is connected to the first access transistor. The second bit cell comprises a second access transistor and a second MTJ stack. The second MTJ stack comprises a second pinned layer and a second free layer, wherein the second free layer is connected to the second access transistor.Type: GrantFiled: January 31, 2020Date of Patent: March 30, 2021Assignee: GLOBALFOUNDRIES U.S. INC.Inventors: Akhilesh Jaiswal, Ajey Poovannummoottil Jacob, Steven Soss
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Patent number: 10515679Abstract: A magneto-resistive memory (MRM) structure includes a source line and a first transistor that includes a source region and a drain region. The source line is electrically connected to the source region of the first transistor. The MRM structure further includes an MRM cell that includes an MRM transistor electrically in series with an MRM magnetic tunnel junction (MTJ). The MRM transistor is electrically connected to the drain region of the first transistor such that the MRM cell is electrically in series with the first transistor. Still further, the MRM structure further includes a voltage amplifier electrically connected to a mid-point node of the first transistor and the MRM transistor, a sense-amplifier electrically connected to the voltage amplifier, and a bit line electrically connected to the MRM MTJ of the MRM cell.Type: GrantFiled: February 6, 2018Date of Patent: December 24, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Akhilesh Jaiswal, Ajey P. Jacob, Bipul C. Paul, William Taylor, Danny Pak-Chum Shum
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Patent number: 10510392Abstract: Integrated circuits, memory arrays and methods for operating integrated circuit devices are provided. In an embodiment, an integrated circuit includes a selected column of bit cells, wherein each bit cell in the selected column is coupled to a source line and coupled to a bit line. Further, the integrated circuit includes a first column of bit cells laterally adjacent the selected column, wherein each bit cell in the first column is coupled to the source line. Also, the integrated circuit includes a second column of bit cells laterally adjacent the selected column, wherein each bit cell in the second column is coupled to the bit line.Type: GrantFiled: July 27, 2018Date of Patent: December 17, 2019Assignee: GLOBALFOUNDRIES, INC.Inventors: Bipul C. Paul, Akhilesh Jaiswal, Ajey Poovannummoottil Jacob, William Taylor, Danny Pak-Chum Shum
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Patent number: 10468083Abstract: Integrated circuits and methods of operating and producing the same are provided. In an exemplary embodiment, an integrated circuit includes a look up table with a first and second memory cell. The first memory cell includes a first magneto electric (ME) layer, a first free layer adjacent to the first ME layer, and a first fixed layer. The second memory cell includes a second ME layer, a second free layer adjacent to the second ME layer, and a second fixed layer. A first word line is in direct communication with the first and second free layers, wherein direct communication is a connection through zero, one, or more intervening components that are electrical conductors. A first bit line is in direct communication with the first ME layer, and a second bit line is in direct communication with the second ME layer.Type: GrantFiled: June 18, 2018Date of Patent: November 5, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Akhilesh Jaiswal, Ajey Poovannummoottil Jacob
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Publication number: 20190244650Abstract: A magneto-resistive memory (MRM) structure includes a source line and a first transistor that includes a source region and a drain region. The source line is electrically connected to the source region of the first transistor. The MRM structure further includes an MRM cell that includes an MRM transistor electrically in series with an MRM magnetic tunnel junction (MTJ). The MRM transistor is electrically connected to the drain region of the first transistor such that the MRM cell is electrically in series with the first transistor. Still further, the MRM structure further includes a voltage amplifier electrically connected to a mid-point node of the first transistor and the MRM transistor, a sense-amplifier electrically connected to the voltage amplifier, and a bit line electrically connected to the MRM MTJ of the MRM cell.Type: ApplicationFiled: February 6, 2018Publication date: August 8, 2019Inventors: Akhilesh Jaiswal, Ajey P. Jacob, Bipul C. Paul, William Taylor, Danny Pak-Chum Shum