Abstract: A sensing circuit for detecting hardware trojans in a target integrated circuit is provided. The sensing circuit includes an array of magnetic tunnel junction circuits where each magnetic tunnel junction circuit including one or more magnetic tunnel junctions. Characteristically, each magnetic tunnel junction circuit configured to provide data for and/or determine a temperature map or a current map of the target integrated circuit.

Abstract: An ultrafast non-volatile memory cell for wafer-scale integration includes a voltage divider that outputs an output voltage. The voltage divider includes a reference resistive device that is a reference magnetic tunnel junction or another reference resistive component and a switchable magnetic tunnel junction that includes a free magnet and a fixed magnet. The switchable magnetic tunnel junction configured such that the free magnet is light switchable between a high impedance state and a low impedance state upon application of an electric signal and incident light. A transistor switch is configured to activate the voltage divider for memory write and read operations. A light modulator is in electrical communication with the output voltage from the voltage divider. The light modulator is configured to modulate a guided light beam for memory read operations. Arrays of the memory cells are also provided.

Abstract: Provided is a device, device for analyte detection, comprising: a first waveguide; a sensor ring resonator, optically coupled to the first waveguide, wherein the sensor ring resonator is sensitive to an analyte; multiple filter ring resonators optically coupled to the sensor ring resonator, one or more detectors, wherein each of the multiple filter ring resonators is optically coupled to at least one of the one or more detectors; and at least a first microfluidic channel, wherein the first microfluidic channel configured to fluidically deliver an analyte to the sensor ring resonator.

Abstract: A method for assuring that integrated circuits are free of malicious circuit insertions and/or IC design modifications through mask swapping/addition is provided. The method includes a step of comparing 3D tomographic images constructed from design GDS to the 3D tomographic images constructed from in-line fab metrology data.

Abstract: Provided is a device, including: an analog optical interconnect; an input array coupled to the analog optical interconnect; and an analog or mixed signal processor or a memory array coupled to the input array via the analog optical interconnect.

Abstract: Provided is an integrated circuit comprising: an amplifier; a sensor electrically connected to a first input of the amplifier; and a set of weights electrically connected to a second input of the amplifier, wherein the amplifier is configured weight an output of the sensor according to an output of the set of weights. Provided is an array of integrated circuits comprising an amplifier; a sensor electrically connected to a first input of the amplifier; and a set of weights electrically connected to a second input of the amplifier, wherein the amplifier is configured weight an output of the sensor according to an output of the set of weights.

Abstract: An in-memory vector addition method for a dynamic random access memory (DRAM) is disclosed which includes consecutively transposing two numbers across a plurality of rows of the DRAM, each number transposed across a fixed number of rows associated with a corresponding number of bits, assigning a scratch-pad including two consecutive bits for each bit of each number being added, two consecutive bits for carry-in (Cin), and two consecutive bits for carry-out-bar (Cout), assigning a plurality of bits in a transposed orientation to hold results as a sum of the two numbers, for each bit position of the two numbers: computing the associated sum of the bit position; and placing the computed sum in the associated bit of the sum.

Abstract: A novel approach for improving the power, performance, area metric for AI computations by dynamically augmenting (doubling) the memory storage capacity uses novel eight transistor SRAM bit-cells.

Abstract: Provided is an optical coupler comprising: an optical fiber housing, the housing configured to accept one or more optical fiber pigtails and the housing mechanically coupled to a backside of an integrated circuit chip; a grating coupler, the grating coupler optically coupled to an output of the one or more optical fiber pigtails of the fiber optic cable housing; and a waveguide, the waveguide optically coupled to an output of the grating coupler, and method of forming same.

Abstract: Provided is an integrated circuit comprising: a sensor structure; a set of weighting elements, each configured to weight an output of the sensor structure; and an output element, the output element configured to collect weighted outputs of the set of weighting elements.

Abstract: An ultrafast non-volatile memory cell for wafer-scale integration includes a voltage divider that outputs an output voltage. The voltage divider includes a reference resistive device that is a reference magnetic tunnel junction or another reference resistive component and a switchable magnetic tunnel junction that includes a free magnet and a fixed magnet. The switchable magnetic tunnel junction configured such that the free magnet is light switchable between a high impedance state and a low impedance state upon application of an electric signal and incident light. A transistor switch is configured to activate the voltage divider for memory write and read operations. A light modulator is in electrical communication with the output voltage from the voltage divider. The light modulator is configured to modulate a guided light beam for memory read operations. Arrays of the memory cells are also provided.

Abstract: Provided is an electro-optic transducer comprising: a first optical disk resonator and a second optical disk resonator, wherein the first optical disk resonator and the second optical disk resonator are optically coupled; a waveguide, the waveguide optically coupled to at least one of the first optical disk resonator and the second optical disk resonator; and a resonator, the resonator functionally coupled to at least a portion of the first optical disk resonator and the second optical disk resonator..

Abstract: An in-memory vector addition method for a dynamic random access memory (DRAM) is disclosed which includes consecutively transposing two numbers across a plurality of rows of the DRAM, each number transposed across a fixed number of rows associated with a corresponding number of bits, assigning a scratch-pad including two consecutive bits for each bit of each number being added, two consecutive bits for carry-in (Cin), and two consecutive bits for carry-out-bar (Cout), assigning a plurality of bits in a transposed orientation to hold results as a sum of the two numbers, for each bit position of the two numbers: computing the associated sum of the bit position; and placing the computed sum in the associated bit of the sum.

Abstract: A sensing circuit for detecting hardware trojans in a target integrated circuit is provided. The sensing circuit includes an array of magnetic tunnel junction circuits where each magnetic tunnel junction circuit including one or more magnetic tunnel junctions. Characteristically, each magnetic tunnel junction circuit configured to provide data for and/or determine a temperature map or a current map of the target integrated circuit.

Abstract: An in-memory vector addition method for a dynamic random access memory (DRAM) is disclosed which includes consecutively transposing two numbers across a plurality of rows of the DRAM, each number transposed across a fixed number of rows associated with a corresponding number of bits, assigning a scratch-pad including two consecutive bits for each bit of each number being added, two consecutive bits for carry-in (Cin), and two consecutive bits for carry-out-bar (Cout), assigning a plurality of bits in a transposed orientation to hold results as a sum of the two numbers, for each bit position of the two numbers: computing the associated sum of the bit position; and placing the computed sum in the associated bit of the sum.

Abstract: Disclosed are embodiments of an integrated circuit structure (e.g., a processing chip), which includes an array of integrated pixel and memory cells configured for deep in-sensor, in-memory computing (e.g., of neural networks). Each cell incorporates a memory structure (e.g., DRAM structure or a ROM structure) with a storage node, which stores a first data value (e.g., a binary weight value), and a sensor connected to a sense node, which outputs a second data value (e.g., an analog input value). Each cell is selectively operable in a functional computing mode during which the voltage level on a bit line is adjusted as a function of both the first data value and the second data value. Each cell is further selectively operable in a storage node read mode. Furthermore, depending upon the type of memory structure (e.g., a DRAM structure), each cell is selectively operable in a storage node write mode.

Abstract: Disclosed is a cell that integrates a pixel and a two-terminal non-volatile memory device. The cell can be selectively operated in write, read and functional computing modes. In the write mode, a first data value is stored the memory device. In the read mode, it is read from the memory device. In the functional computing mode, the pixel captures a second data value and a sensed change in an electrical parameter (e.g., voltage or current) on a bitline connected to the cell is a function of both the first and second data value. Also disclosed is an IC structure that includes an array of the cells and, when multiple cells in a given column are concurrently operated in the functional computing mode, the sensed total change in the electrical parameter on the bitline for the column is indicative of a result of a dot product computation.

Abstract: A method for assuring that integrated circuits are free of malicious circuit insertions and/or IC design modifications through mask swapping/addition is provided. The method includes a step of comparing 3D tomographic images constructed from design GDS to the 3D tomographic images constructed from in-line fab metrology data.

Abstract: Disclosed is a reference circuit having an even number m of groups of m parallel-connected magnetic tunnel junctions (MTJs). The MTJs in half of the groups are programmed to have parallel resistances (RP) and the MTJs in the other half are programmed to have anti-parallel resistances (RAP). Switches connect the groups in series, creating a series-parallel resistor network. The total resistance (RT) of the network has low variability and is essentially equal to half the sum of a nominal RP plus a nominal RAP and can be employed as a reference resistance (RREF). Under specific biasing conditions the series-parallel resistor network can generate a low variability reference parameter (XREF) that is dependent on this RREF. Also disclosed are an integrated circuit (IC) that includes the reference circuit and a magnetic random access memory (MRAM) structure, which uses XREF to determine stored data values in MRAM cells and associated methods.

Abstract: Disclosed is a cell that integrates a pixel and a two-terminal non-volatile memory device. The cell can be selectively operated in write, read and functional computing modes. In the write mode, a first data value is stored the memory device. In the read mode, it is read from the memory device. In the functional computing mode, the pixel captures a second data value and a sensed change in an electrical parameter (e.g., voltage or current) on a bitline connected to the cell is a function of both the first and second data value. Also disclosed is an IC structure that includes an array of the cells and, when multiple cells in a given column are concurrently operated in the functional computing mode, the sensed total change in the electrical parameter on the bitline for the column is indicative of a result of a dot product computation.