Patents by Inventor AKHILESH K. SINGH
AKHILESH K. SINGH has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10217698Abstract: A method for forming a packaged semiconductor device includes attaching a first major surface of a semiconductor die to a plurality of protrusions extending from a package substrate. A top surface of each protrusion has a die attach material, and the plurality of protrusions define an open region between the first major surface of the semiconductor die and the package substrate. Interconnects are formed between a second major surface of the semiconductor die and the package substrate in which the second major surface opposite the first major surface. An encapsulant material is formed over the semiconductor die and the interconnects.Type: GrantFiled: December 19, 2016Date of Patent: February 26, 2019Assignee: NXP USA, Inc.Inventors: Akhilesh K. Singh, Rama I. Hegde, Nishant Lakhera
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Patent number: 10211184Abstract: A packaged semiconductor device includes a first package substrate having a first plurality of lead fingers, a first die attached to a first major surface of the first package substrate, a second package substrate having a second plurality of lead fingers, wherein each of the second plurality of lead fingers extends over the first die and the second package substrate is electrically isolated from the first package substrate. The device also includes a second die attached to a first major surface of the second package substrate, over the first die, and an encapsulant surrounding the first die, the first package substrate, the second die, and the second package substrate, wherein the encapsulant exposes a portion of the first package substrate and a portion of the second package substrate.Type: GrantFiled: November 3, 2017Date of Patent: February 19, 2019Assignee: NXP USA, Inc.Inventors: Nishant Lakhera, Navas Khan Oratti Kalandar, Akhilesh K. Singh
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Patent number: 10147645Abstract: A method of processing a semiconductor wafer includes forming a plurality of die in the semiconductor wafer. The semiconductor wafer has a first brittleness. The top surface the semiconductor wafer undergoes grinding to leave an inner planar surface and a rim, wherein the rim extends above the inner planar surface and around a perimeter of the grinded semiconductor wafer. The first encapsulant material is formed over the inner planar surface and contained within the rim to form a composite semiconductor wafer that has a second brittleness less than the first brittleness. The composite semiconductor wafer is singulated into the plurality of die in which each die of the plurality of die is a composite structure die.Type: GrantFiled: September 22, 2015Date of Patent: December 4, 2018Assignee: NXP USA, Inc.Inventors: Navas Khan Oratti Kalandar, Nishant Lakhera, Akhilesh K. Singh
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Patent number: 9978614Abstract: A packaged semiconductor device includes a substrate, an electronic device coupled to the substrate, encapsulant including a first major surface surrounding the electronic device, and an oxygen barrier layer within fifty percent of a thickness of the encapsulant from a second major surface of the encapsulant. The oxygen barrier covers at least a portion of an area of the second major surface of the encapsulant to help reduce or eliminate warping of the encapsulant and/or the substrate of the packaged semiconductor device due to oxidation. A thickness of the oxygen barrier layer is less than 100 microns.Type: GrantFiled: June 24, 2016Date of Patent: May 22, 2018Assignee: NXP USA, Inc.Inventors: Nishant Lakhera, James R. Guajardo, Varughese Mathew, Akhilesh K. Singh
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Publication number: 20180053749Abstract: A packaged semiconductor device includes a first package substrate having a first plurality of lead fingers, a first die attached to a first major surface of the first package substrate, a second package substrate having a second plurality of lead fingers, wherein each of the second plurality of lead fingers extends over the first die and the second package substrate is electrically isolated from the first package substrate. The device also includes a second die attached to a first major surface of the second package substrate, over the first die, and an encapsulant surrounding the first die, the first package substrate, the second die, and the second package substrate, wherein the encapsulant exposes a portion of the first package substrate and a portion of the second package substrate.Type: ApplicationFiled: November 3, 2017Publication date: February 22, 2018Inventors: Nishant LAKHERA, Navas Khan Oratti KALANDAR, Akhilesh K. SINGH
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Publication number: 20170278825Abstract: A packaged semiconductor device includes a first package substrate having a first plurality of lead fingers, a first die attached to a first major surface of the first package substrate, a second package substrate having a second plurality of lead fingers, wherein each of the second plurality of lead fingers extends over the first die and the second package substrate is electrically isolated from the first package substrate. The device also includes a second die attached to a first major surface of the second package substrate, over the first die, and an encapsulant surrounding the first die, the first package substrate, the second die, and the second package substrate, wherein the encapsulant exposes a portion of the first package substrate and a portion of the second package substrate.Type: ApplicationFiled: March 24, 2016Publication date: September 28, 2017Inventors: Nishant LAKHERA, Navas Khan ORATTI KALANDAR, Akhilesh K. SINGH
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Patent number: 9691637Abstract: A method of fabricating a plurality of semiconductor devices includes attaching a plurality of integrated circuit (IC) die to a substrate including forming electric connections between contacts on the IC die and contacts on the substrate. After the IC die is attached to the substrate, a first encapsulating material is placed over stress-sensitive areas of the IC die. The first encapsulating material includes thirty percent or less of filler particles greater than a specified size. A second encapsulating material is placed over the first encapsulating material. The second encapsulating material includes sixty percent or more of filler particles.Type: GrantFiled: October 7, 2015Date of Patent: June 27, 2017Assignee: NXP USA, INC.Inventors: Navas Khan Oratti Kalandar, Nishant Lakhera, Akhilesh K. Singh
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Publication number: 20170103905Abstract: A method of fabricating a plurality of semiconductor devices includes attaching a plurality of integrated circuit (IC) die to a substrate including forming electric connections between contacts on the IC die and contacts on the substrate. After the IC die is attached to the substrate, a first encapsulating material is placed over stress-sensitive areas of the IC die. The first encapsulating material includes thirty percent or less of filler particles greater than a specified size. A second encapsulating material is placed over the first encapsulating material. The second encapsulating material includes sixty percent or more of filler particles.Type: ApplicationFiled: October 7, 2015Publication date: April 13, 2017Inventors: NAVAS KHAN ORATTI KALANDAR, NISHANT LAKHERA, AKHILESH K. SINGH
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Publication number: 20170098597Abstract: A method for forming a packaged semiconductor device includes attaching a first major surface of a semiconductor die to a plurality of protrusions extending from a package substrate. A top surface of each protrusion has a die attach material, and the plurality of protrusions define an open region between the first major surface of the semiconductor die and the package substrate. Interconnects are formed between a second major surface of the semiconductor die and the package substrate in which the second major surface opposite the first major surface. An encapsulant material is formed over the semiconductor die and the interconnects.Type: ApplicationFiled: December 19, 2016Publication date: April 6, 2017Inventors: AKHILESH K. SINGH, RAMA I. HEGDE, NISHANT LAKHERA
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Publication number: 20170084491Abstract: A method of processing a semiconductor wafer includes forming a plurality of die in the semiconductor wafer. The semiconductor wafer has a first brittleness. The top surface the semiconductor wafer undergoes grinding to leave an inner planar surface and a rim, wherein the rim extends above the inner planar surface and around a perimeter of the grinded semiconductor wafer. The first encapsulant material is formed over the inner planar surface and contained within the rim to form a composite semiconductor wafer that has a second brittleness less than the first brittleness. The composite semiconductor wafer is singulated into the plurality of die in which each die of the plurality of die is a composite structure die.Type: ApplicationFiled: September 22, 2015Publication date: March 23, 2017Inventors: NAVAS KHAN ORATTI KALANDAR, NISHANT LAKHERA, AKHILESH K. SINGH
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Patent number: 9598280Abstract: A device in which an electronic circuit positioned within a cavity of a package housing is encased by a bubble restrictor material, with a media resistant material overlaying the bubble restrictor material. The bubble restrictor material functions to inhibit the formation and growth of moisture-related bubbles within the material, including at the interfaces of the material and surfaces within the package housing. The media resistant material is resistant to physical and chemical alterations by media within an external environment to which the device is exposed. The media resistant material and bubble resistant material function to transfer a sensed characteristic of the media to the electronic circuit.Type: GrantFiled: November 10, 2014Date of Patent: March 21, 2017Assignee: NXP USA, Inc.Inventors: Akhilesh K. Singh, Dwight L. Daniels, Darrel R. Frear, Stephen R. Hooper
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Patent number: 9559077Abstract: A method for forming a packaged semiconductor device includes attaching a first major surface of a semiconductor die to a plurality of protrusions extending from a package substrate. A top surface of each protrusion has a die attach material, and the plurality of protrusions define an open region between the first major surface of the semiconductor die and the package substrate. Interconnects are formed between a second major surface of the semiconductor die and the package substrate in which the second major surface opposite the first major surface. An encapsulant material is formed over the semiconductor die and the interconnects.Type: GrantFiled: October 22, 2014Date of Patent: January 31, 2017Assignee: NXP USA, Inc.Inventors: Akhilesh K. Singh, Rama I. Hegde, Nishant Lakhera
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Patent number: 9508632Abstract: A semiconductor structure includes a lead frame having a flag and a plurality of leads, a semiconductor die attached to a first major surface of the flag, and a plurality of re-routed lead fingers attached to the lead frame. The plurality of leads has a first pitch. The first end of each re-routed lead finger is attached to a lead of the plurality of leads. Each re-routed lead finger extends over the semiconductor die such that a second end of each re-routed lead finger is over and spaced apart from the flag of the lead frame. The second ends of the plurality of re-routed lead fingers has a second pitch different from the first pitch.Type: GrantFiled: June 24, 2015Date of Patent: November 29, 2016Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Navas Khan Oratti Kalandar, Nishant Lakhera, Varughese Mathew, Akhilesh K. Singh
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Publication number: 20160307780Abstract: A packaged semiconductor device includes a substrate, an electronic device coupled to the substrate, encapsulant including a first major surface surrounding the electronic device, and an oxygen barrier layer within fifty percent of a thickness of the encapsulant from a second major surface of the encapsulant. The oxygen barrier covers at least a portion of an area of the second major surface of the encapsulant to help reduce or eliminate warping of the encapsulant and/or the substrate of the packaged semiconductor device due to oxidation. A thickness of the oxygen barrier layer is less than 100 microns.Type: ApplicationFiled: June 24, 2016Publication date: October 20, 2016Inventors: Nishant LAKHERA, JAMES R. GUAJARDO, VARUGHESE MATHEW, AKHILESH K. SINGH
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Publication number: 20160130136Abstract: A device in which an electronic circuit positioned within a cavity of a package housing is encased by a bubble restrictor material, with a media resistant material overlaying the bubble restrictor material. The bubble restrictor material functions to inhibit the formation and growth of moisture-related bubbles within the material, including at the interfaces of the material and surfaces within the package housing. The media resistant material is resistant to physical and chemical alterations by media within an external environment to which the device is exposed. The media resistant material and bubble resistant material function to transfer a sensed characteristic of the media to the electronic circuit.Type: ApplicationFiled: November 10, 2014Publication date: May 12, 2016Inventors: AKHILESH K. SINGH, DWIGHT L. DANIELS, DARREL R. FREAR, STEPHEN R. HOOPER
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Publication number: 20160118365Abstract: A method for forming a packaged semiconductor device includes attaching a first major surface of a semiconductor die to a plurality of protrusions extending from a package substrate. A top surface of each protrusion has a die attach material, and the plurality of protrusions define an open region between the first major surface of the semiconductor die and the package substrate. Interconnects are formed between a second major surface of the semiconductor die and the package substrate in which the second major surface opposite the first major surface. An encapsulant material is formed over the semiconductor die and the interconnects.Type: ApplicationFiled: October 22, 2014Publication date: April 28, 2016Inventors: AKHILESH K. SINGH, RAMA I. HEGDE, NISHANT LAKHERA
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Publication number: 20160064299Abstract: A packaged semiconductor device includes a substrate, an electronic device coupled to the substrate, encapsulant including a first major surface surrounding the electronic device, and an oxygen barrier layer within fifty percent of a thickness of the encapsulant from a second major surface of the encapsulant. The oxygen barrier covers at least a portion of an area of the second major surface of the encapsulant to help reduce or eliminate warping of the encapsulant and/or the substrate of the packaged semiconductor device due to oxidation. A thickness of the oxygen barrier layer is less than 100 microns.Type: ApplicationFiled: August 29, 2014Publication date: March 3, 2016Inventors: NISHANT LAKHERA, JAMES R. GUAJARDO, VARUGHESE MATHEW, AKHILESH K. SINGH