Abstract: Disclosed is a memory structure with reference-free single-ended sensing. The structure includes an array of non-volatile memory (NVM) cells (e.g., resistance programmable NVM cells) and a sense circuit connected to the array via a data line and a column decoder. The sense circuit includes field effect transistors (FETs) connected in parallel between an output node and a switch and inverters connected between the data line and the gates of the FETs, respectively. To determine the logic value of a stored bit, the inverters are used to detect whether or not a voltage drop occurs on the data line within a predetermined period of time. Using redundant inverters to control redundant FETs connected to the output node increases the likelihood that the occurrence of the voltage drop will be detected and captured at the output node, even in the presence of process and/or thermal variations. Also disclosed is a sensing method.

Abstract: Disclosed is a memory structure with reference-free single-ended sensing. The structure includes an array of non-volatile memory (NVM) cells (e.g., resistance programmable NVM cells) and a sense circuit connected to the array via a data line and a column decoder. The sense circuit includes field effect transistors (FETs) connected in parallel between an output node and a switch and inverters connected between the data line and the gates of the FETs, respectively. To determine the logic value of a stored bit, the inverters are used to detect whether or not a voltage drop occurs on the data line within a predetermined period of time. Using redundant inverters to control redundant FETs connected to the output node increases the likelihood that the occurrence of the voltage drop will be detected and captured at the output node, even in the presence of process and/or thermal variations. Also disclosed is a sensing method.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to optical neuro-mimetic devices and methods of manufacture. The structure includes: a plurality of photodetectors and electrical circuitry that converts photocurrent generated from the photodetectors into electrical current and then sums up the electrical current to mimic neural functionality.

Abstract: The present disclosure relates to a structure including a latch circuit, a first non-volatile field effect transistor (FET) connecting to a first side of the latch circuit and a bit line, and a second non-volatile field effect transistor (FET) connecting to a second side of the latch circuit and a complementary bit line.

Abstract: The present disclosure relates to a structure including a latch circuit, a first non-volatile field effect transistor (FET) connecting to a first side of the latch circuit and a bit line, and a second non-volatile field effect transistor (FET) connecting to a second side of the latch circuit and a complementary bit line.

Abstract: The present disclosure relates to a structure including a plurality of magnetic random access memory (MRAM) bitcells including a first circuit and a second circuit, the second circuit being connected to a same wordline as the first circuit such that the second circuit is configured as a parallel series connection to generate a reference resistance value for sensing.

Abstract: An image sensor includes an array of optically switchable magnetic tunnel junctions (MTJs) arranged in columns and rows. The image sensor has first lines of transparent conductive material and second lines of conductive material. Each first line is in contact with the free layers of the MTJs in a corresponding row. Each second line is electrically connected to the fixed layers MTJs in a corresponding column. The first lines are concurrently exposable to radiation. The first and second lines are selectively biasable. In a global reset operation, biasing conditions are such that all MTJs are switched to an anti-parallel state. In a global sense operation, biasing conditions are such that, depending upon the intensity of radiation received at those portions of the first lines in contact with MTJs, the MTJs may switch to a parallel state. In selective read operations, biasing conditions are such that stored data values in the MTJs can be read.

Abstract: An image sensor includes an array of optically switchable magnetic tunnel junctions (MTJs) arranged in columns and rows. The image sensor has first lines of transparent conductive material and second lines of conductive material. Each first line is in contact with the free layers of the MTJs in a corresponding row. Each second line is electrically connected to the fixed layers MTJs in a corresponding column. The first lines are concurrently exposable to radiation. The first and second lines are selectively biasable. In a global reset operation, biasing conditions are such that all MTJs are switched to an anti-parallel state. In a global sense operation, biasing conditions are such that, depending upon the intensity of radiation received at those portions of the first lines in contact with MTJs, the MTJs may switch to a parallel state. In selective read operations, biasing conditions are such that stored data values in the MTJs can be read.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to optical neuro-mimetic devices and methods of manufacture. The structure includes: a plurality of photodetectors and electrical circuitry that converts photocurrent generated from the photodetectors into electrical current and then sums up the electrical current to mimic neural functionality.

Abstract: The disclosure provides a circuit structure and method for memory storage using a memory cell and magnetic random access memory (MRAM) stack. A circuit structure includes a memory cell having a first latch configured to store a digital bit, a first diode coupled to the first latch, and a first magnetic random access memory (MRAM) stack coupled to the first latch of the memory cell through the first diode. The first MRAM stack includes a first layer and a second layer each having a respective magnetic moment. The magnetic moment of the second layer is adjustable between a parallel orientation and an antiparallel orientation with respect to the magnetic moment of the first layer. Further, the magnetic anisotropy of the second layer can be modified through application of an applied voltage (VCMA effect). A spin Hall electrode is directly coupled to the first MRAM stack.

Abstract: The present disclosure relates to a structure including a memory array circuit with a magnetic tunnel junction array and an inverter between at least two data magnetic tunnel junctions and configured to enable logic-in-memory computations.

Abstract: The present disclosure relates to a structure including a memory array circuit with a magnetic tunnel junction array and an inverter between at least two data magnetic tunnel junctions and configured to enable logic-in-memory computations.