Abstract: Disclosed are methods, systems and devices for operation of memory device. In one aspect, volatile memory bitcells and non-volatile memory bitcells may be integrated to facilitate transfer of stored values between the volatile and non-volatile memory bitcells.

Abstract: Disclosed are methods, systems and devices for operation of memory device. In one aspect, volatile memory bitcells and non-volatile memory bitcells may be integrated to facilitate transfer of stored values between the volatile and non-volatile memory bitcells.

Abstract: Disclosed are techniques for forming and operating magnetic memory devices.

Abstract: Disclosed are methods, systems and devices for operation of memory device. In one aspect, volatile memory bitcells and non-volatile memory bitcells may be integrated to facilitate transfer of stored values between the volatile and non-volatile memory bitcells.

Abstract: In a particular implementation, a method of storing dynamic random-access memory (DRAM) data in respective magneto-electric magnetic tunnel junctions (ME-MTJ) of D-MRAM bit-cells of a D-MRAM bit-cell memory array, the method comprising: for each of the D-MRAM bit-cells: writing a first data value in a storage capacitor; and in a first cycle, providing a first voltage to a source line coupled to an ME-MTJ, wherein in response to the storage capacitor storing the first data value, the ME-MTJ is configured to store the first data value if the first voltage generates a voltage difference between first and second terminals of the ME-MTJ.

Abstract: In a particular implementation, a method of storing dynamic random-access memory (DRAM) data in respective magneto-electric magnetic tunnel junctions (ME-MTJ) of D-MRAM bit-cells of a D-MRAM bit-cell memory array, the method comprising: for each of the D-MRAM bit-cells: writing a first data value in a storage capacitor; and in a first cycle, providing a first voltage to a source line coupled to an ME-MTJ, wherein in response to the storage capacitor storing the first data value, the ME-MTJ is configured to store the first data value if the first voltage generates a voltage difference between first and second terminals of the ME-MTJ.

Abstract: Briefly, embodiments of claimed subject matter relate to backup of parameters, such as binary logic values, stored in nonvolatile memory, such as one or more SRAM cells. Binary logic values from a SRAM cell, for example, may be stored utilizing resistance states of a magnetic random-access memory (MRAM) element. Parameters stored in one or more MRAM elements may be restored to SRAM memory cells following a backup.

Abstract: A method of obtaining an in-memory vector-based dot product is disclosed, which includes providing a matrix of memory cells having M rows, each memory cell in each row holding a value and having dedicated read transistors T1 and T2, where T1 is controlled by the value held in the associated memory cell and T2 is controlled by a row-dedicated source (vin) for each row, the combination of the T1 and T2 transistors for each cell selectively (i) couple a reference voltage with a column-dedicated read bit line (RBL) for each column for an in-memory vector-based dot product operation or (ii) couple ground with the column-dedicated read bit line (RBL) for each column for a memory read operation, where total resistance of the read transistors (R) for each cell in each row is based on Rmax/2(M-1), . . . Rmax, where Rmax is the resistance of the least significant cell in each row.

Abstract: An in-situ in-memory implication gate is disclosed. The gate include a memory cell. The cell includes a first voltage source, a second voltage source lower in value than the first voltage source, a first and second magnetic tunneling junction devices (MTJ) selectively juxtaposed in a series and mirror imaged relationship between the first and second sources, each having a pinned layer (PL) in a first direction and a free layer (FL) having a polarity that can be switched from the first direction in which case the MTJ is in a parallel configuration presenting an electrical resistance to current flow below a first resistance threshold to a second direction in which case the MTJ is in an anti-parallel configuration presenting an electrical resistance to current flow higher than a second resistance threshold, and further each having a non-magnetic layer (NML) separating the PL from the FL.

Abstract: In a particular implementation, a method to perform a read operation on a voltage divider bit-cell having first and second transistors and first and second storage elements is disclosed. The method includes: providing a first voltage to a bit-line coupled to the second transistor of the voltage-divider bit-cell; providing a second voltage to a first word-line and providing an electrical grounding to a second word-line; where the first and second word-lines are coupled to the respective first and second resistive memory devices; and determining at least one of first and second data resistances in the respective first and second storage elements based on an output voltage on the bit-line.

Abstract: In a particular implementation, a method to perform a read operation on a voltage divider bit-cell having first and second transistors and first and second storage elements is disclosed. The method includes: providing a first voltage to a bit-line coupled to the second transistor of the voltage-divider bit-cell; providing a second voltage to a first word-line and providing an electrical grounding to a second word-line; where the first and second word-lines are coupled to the respective first and second resistive memory devices; and determining at least one of first and second data resistances in the respective first and second storage elements based on an output voltage on the bit-line.

Abstract: A method of obtaining an in-memory vector-based dot product is disclosed, which includes providing a matrix of memory cells having M rows, each memory cell in each row holding a value and having dedicated read transistors T1 and T2, where T1 is controlled by the value held in the associated memory cell and T2 is controlled by a row-dedicated source (vin) for each row, the combination of the T1 and T2 transistors for each cell selectively (i) couple a reference voltage with a column-dedicated read bit line (RBL) for each column for an in-memory vector-based dot product operation or (ii) couple ground with the column-dedicated read bit line (RBL) for each column for a memory read operation, where total resistance of the read transistors (R) for each cell in each row is based on Rmax/2(M-1), . . . Rmax, where Rmax is the resistance of the least significant cell in each row.

Abstract: Disclosed are techniques for forming and operating magnetic memory devices.

Abstract: Briefly, embodiments of claimed subject matter relate to backup of parameters, such as binary logic values, stored in nonvolatile memory, such as one or more SRAM cells. Binary logic values from a SRAM cell, for example, may be stored utilizing resistance states of a magnetic random-access memory (MRAM) element. Parameters stored in one or more MRAM elements may be restored to SRAM memory cells following a backup.

Abstract: In a particular implementation, a method to perform a read operation on a magneto-resistive random-access memory (MRAM) bit-cell includes: providing a voltage signal across one or more storage elements of the MRAM bit-cell, determining an electrical resistance of the one or more storage elements of the MRAM bit-cell, and removing the voltage signal from the MRAM bit-cell prior to an end of an incubation delay interval.

Abstract: Disclosed are methods, systems and devices for operation of memory device. In one aspect, volatile memory bitcells and non-volatile memory bitcells may be integrated to facilitate transfer of stored values between the volatile and non-volatile memory bitcells.

Abstract: An in-situ in-memory implication gate is disclosed. The gate include a memory cell. The cell includes a first voltage source, a second voltage source lower in value than the first voltage source, a first and second magnetic tunneling junction devices (MTJ) selectively juxtaposed in a series and mirror imaged relationship between the first and second sources, each having a pinned layer (PL) in a first direction and a free layer (FL) having a polarity that can be switched from the first direction in which case the MTJ is in a parallel configuration presenting an electrical resistance to current flow below a first resistance threshold to a second direction in which case the MTJ is in an anti-parallel configuration presenting an electrical resistance to current flow higher than a second resistance threshold, and further each having a non-magnetic layer (NML) separating the PL from the FL.