Patents by Inventor Akhilesh YADAV

Akhilesh YADAV has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11513963
    Abstract: A data storage device and method for application identifier handler heads-up for faster storage response are provided. In one embodiment, a data storage device is provided comprising a volatile memory, a non-volatile memory, and a controller. The controller is configured to: receive data and a logical address from a host, wherein the data is tagged with an identifier of an application on the host; store the data at a physical address in the non-volatile memory; maintain a logical-to-physical address table that comprises an entry associating the logical address, physical address, and identifier; determine that the application is subsequently reloaded on the host; and cache, in the volatile memory, a portion of the logical-to-physical address table that comprises the entry for the identifier. Other embodiments are provided.
    Type: Grant
    Filed: March 11, 2021
    Date of Patent: November 29, 2022
    Assignee: Western Digital Technologies. Inc.
    Inventors: Ramanathan Muthiah, Akhilesh Yadav
  • Publication number: 20220308798
    Abstract: An integrated memory assembly comprises a memory die and a control die bonded to the memory die. The memory die includes a memory structure of non-volatile memory cells. The control die is configured to program user data to and read user data from the memory die in response to commands from a memory controller. To utilize space more efficiently on the memory die, the control die compacts fragmented data on the memory die.
    Type: Application
    Filed: June 10, 2022
    Publication date: September 29, 2022
    Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Rakesh Balakrishnan, Eldhose Peter, Akhilesh Yadav
  • Publication number: 20220308787
    Abstract: Aspects of a storage device including a memory and a controller are provided. The memory includes a plurality of non-volatile memory packages coupled to the switch, in which each non-volatile memory package includes a plurality of non-volatile memory dies. The controller can select a non-volatile memory package with the switch. The controller can establish a data channel connection between the selected non-volatile memory package and the controller via the switch. In some aspects, the selected non-volatile memory package is transitioned into an active mode and one or more non-selected non-volatile memory packages are each transitioned into a standby mode. The controller also can perform one or more storage device operations with one or more non-volatile memory dies of the plurality of non-volatile memory dies within the selected non-volatile memory package. Thus, the controller may facilitate a switch based ball grid array extension, thereby improving memory capacity of the storage device.
    Type: Application
    Filed: March 29, 2021
    Publication date: September 29, 2022
    Inventors: Akhilesh Yadav, Ramanathan Muthiah, Eldhose Peter
  • Publication number: 20220308769
    Abstract: Aspects of a storage device including a memory and a controller are provided. The memory includes a plurality of non-volatile memory packages coupled to the switch, with each non-volatile memory package including a plurality of non-volatile memory dies. The controller monitors a wear level of each non-volatile memory package in the plurality of non-volatile memory packages connected to the controller via the switch. The controller determines whether a wear level of a first non-volatile memory package of the plurality of non-volatile memory packages exceeds a wear level threshold. The controller also can transfer data from the first non-volatile memory package to a second non-volatile memory package of the plurality of non-volatile memory packages through the switch based on the wear level of the first non-volatile memory package exceeding the wear level threshold. Thus, the controller may facilitate a persistent switch-based storage controller, thereby improving memory capacity of the storage device.
    Type: Application
    Filed: May 5, 2022
    Publication date: September 29, 2022
    Inventors: Ramanathan MUTHIAH, Akhilesh YADAV
  • Publication number: 20220292020
    Abstract: A data storage device and method for application identifier handler heads-up for faster storage response are provided. In one embodiment, a data storage device is provided comprising a volatile memory, a non-volatile memory, and a controller. The controller is configured to: receive data and a logical address from a host, wherein the data is tagged with an identifier of an application on the host; store the data at a physical address in the non-volatile memory; maintain a logical-to-physical address table that comprises an entry associating the logical address, physical address, and identifier; determine that the application is subsequently reloaded on the host; and cache, in the volatile memory, a portion of the logical-to-physical address table that comprises the entry for the identifier. Other embodiments are provided.
    Type: Application
    Filed: March 11, 2021
    Publication date: September 15, 2022
    Applicant: Western Digital Technologies, Inc.
    Inventors: Ramanathan Muthiah, Akhilesh Yadav
  • Publication number: 20220291839
    Abstract: A data storage device including, in one implementation, a non-volatile memory device including a memory block that includes a plurality of memory dies and a controller that is coupled to the non-volatile memory device and that allocates power to non-memory components based on a determined usage of the memory dies. The controller is configured to monitor a utilization of the plurality of memory dies, determine a utilization state of the plurality of memory dies, and calculate an amount of available power allocated to the plurality of memory dies in response to determining that the plurality of memory dies are in a low utilization state. The controller is also configured to determine whether the amount of available power is above a predetermined threshold, and reallocate the available power to one or more components within the data storage device in response to determining that the amount of available power is above the predetermined threshold.
    Type: Application
    Filed: June 2, 2022
    Publication date: September 15, 2022
    Inventors: Amit Sharma, Abhinandan Venugopal, Dinesh Kumar Agarwal, Akhilesh Yadav
  • Patent number: 11392327
    Abstract: An integrated memory assembly comprises a memory die and a control die bonded to the memory die. The memory die includes a memory structure of non-volatile memory cells. The control die is configured to program user data to and read user data from the memory die in response to commands from a memory controller. To utilize space more efficiently on the memory die, the control die compacts fragmented data on the memory die.
    Type: Grant
    Filed: February 17, 2021
    Date of Patent: July 19, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Rakesh Balakrishnan, Eldhose Peter, Akhilesh Yadav
  • Patent number: 11379137
    Abstract: A data storage device including, in one implementation, a non-volatile memory device including a memory block that includes a plurality of memory dies and a controller that is coupled to the non-volatile memory device and that allocates power to non-memory components based on a determined usage of the memory dies. The controller is configured to monitor a utilization of the plurality of memory dies, determine a utilization state of the plurality of memory dies, and calculate an amount of available power allocated to the plurality of memory dies in response to determining that the plurality of memory dies are in a low utilization state. The controller is also configured to determine whether the amount of available power is above a predetermined threshold, and reallocate the available power to one or more components within the data storage device in response to determining that the amount of available power is above the predetermined threshold.
    Type: Grant
    Filed: February 16, 2021
    Date of Patent: July 5, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Amit Sharma, Abhinandan Venugopal, Dinesh Kumar Agarwal, Akhilesh Yadav
  • Publication number: 20220179742
    Abstract: Systems and methods for host-assisted storage device error correction are described. A host may first encode host data with a forward error correction code (ECC) and send the encoded host data to the storage device. The storage device may further encode the host data using its own ECC. The host may also provide the forward ECC parity information to be stored on the storage device in a different location than the host data. When the host data is read by the storage device, the storage device will decode with its ECC. If the storage device ECC decode is incomplete and the bit error rate is below the recoverable error threshold of the forward error correction, the partially-recovered host data will be sent to the host. The host will complete decode using the forward ECC and parity data. Forward ECC may be selectively applied to important host data.
    Type: Application
    Filed: February 16, 2021
    Publication date: June 9, 2022
    Inventors: Akhilesh Yadav, Ramanathan Muthiah
  • Publication number: 20220171970
    Abstract: A storage system and method for event-driven data stitching in surveillance systems are provided. In one embodiment, a storage system is provided comprising a memory and a controller. The controller is configured to track an object in a plurality of video streams; determine which video frames in each of the plurality of video streams contain the object; create a separate video stream from the video frames that contain the object; and store the created separate video stream in the memory. Other embodiments are provided.
    Type: Application
    Filed: February 18, 2021
    Publication date: June 2, 2022
    Applicant: Western Digital Technologies, Inc.
    Inventors: Akhilesh Yadav, Ramanathan Muthiah
  • Patent number: 11340986
    Abstract: Systems and methods for host-assisted storage device error correction are described. A host may first encode host data with a forward error correction code (ECC) and send the encoded host data to the storage device. The storage device may further encode the host data using its own ECC. The host may also provide the forward ECC parity information to be stored on the storage device in a different location than the host data. When the host data is read by the storage device, the storage device will decode with its ECC. If the storage device ECC decode is incomplete and the bit error rate is below the recoverable error threshold of the forward error correction, the partially-recovered host data will be sent to the host. The host will complete decode using the forward ECC and parity data. Forward ECC may be selectively applied to important host data.
    Type: Grant
    Filed: February 16, 2021
    Date of Patent: May 24, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Akhilesh Yadav, Ramanathan Muthiah
  • Publication number: 20220129388
    Abstract: A non-volatile storage system includes a memory controller connected to an integrated memory assembly. The integrated memory assembly includes a memory die comprising non-volatile memory cells and a control die bonded to the memory die. The memory controller receives commands from a host, performs logical address to physical address translation (“address translation”) operations for the commands, and instructs the integrated memory assembly to perform one or more operations in support of the command. The control die also includes the ability to perform the address translation. When performing a command from the host, the memory controller can choose to perform the necessary address translation or instruct the control die to perform the address translation. When the control die performs the address translation, the resulting physical address is used by the control die to perform one or more operations in support of the command.
    Type: Application
    Filed: February 17, 2021
    Publication date: April 28, 2022
    Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Rakesh Balakrishnan, Eldhose Peter, Akhilesh Yadav, Ramanathan Muthiah, Vimal Kumar Jain
  • Publication number: 20220075559
    Abstract: An integrated memory assembly comprises a memory die and a control die bonded to the memory die. The memory die includes a memory structure of non-volatile memory cells. The control die is configured to program user data to and read user data from the memory die in response to commands from a memory controller. To utilize space more efficiently on the memory die, the control die compacts fragmented data on the memory die.
    Type: Application
    Filed: February 17, 2021
    Publication date: March 10, 2022
    Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Rakesh Balakrishnan, Eldhose Peter, Akhilesh Yadav
  • Patent number: 11169584
    Abstract: A dual-connector storage system and method for simultaneously providing power and memory access to a computing device are provided. In one embodiment, the storage system comprises a memory, a first connector, a second connector, and a controller. The controller is configured to provide power received from the second connector to a computing device connected with the first connector while also allowing the computing device to access the memory via the first connector. Other embodiments are provided.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: November 9, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Eldhose Peter, Akhilesh Yadav, Rakesh Balakrishnan
  • Publication number: 20210303047
    Abstract: A dual-connector storage system and method for simultaneously providing power and memory access to a computing device are provided. In one embodiment, the storage system comprises a memory, a first connector, a second connector, and a controller. The controller is configured to provide power received from the second connector to a computing device connected with the first connector while also allowing the computing device to access the memory via the first connector. Other embodiments are provided.
    Type: Application
    Filed: March 31, 2020
    Publication date: September 30, 2021
    Applicant: Western Digital Technologies, Inc.
    Inventors: Eldhose Peter, Akhilesh Yadav, Rakesh Balakrishnan
  • Publication number: 20190336959
    Abstract: The present disclosure provides a process for treatment a spent ionic liquid, comprising: mixing the spent ionic liquid with a first fluid medium and water to obtain slurry comprising a solid fraction and a liquid fraction; separating the solid fraction from slurry to obtain a filtrate and a residue comprising hydrated ionic solids; followed by drying the residue comprising the hydrated ionic solids at a temperature in the range of 60° C. to 120° C. to obtain treated ionic solids; and evaporating the filtrate to recover the fluid medium. The process of the present disclosure further comprises a step of contacting the treated ionic solids with at least one second fluid medium to separate an active ionic liquid.
    Type: Application
    Filed: December 6, 2017
    Publication date: November 7, 2019
    Applicant: Reliance Industries Limited
    Inventors: Vibhuti DUKHANDE, Visvanath KOTRA, Parasuveera UPPARA, Pavankumar ADURI, Suresh IYENGAR, Prashant TANGADE, Akhilesh YADAV
  • Publication number: 20170197994
    Abstract: The instant disclosure relates to liquid salts such as but not limiting to ionic liquids; and method for recovering liquid salts including ionic liquids. Ionic liquids get deactivated due to presence of various contaminants or impurities. The present disclosure deals with recovery and regeneration of ionic liquids using compounds containing at least one coordinating agent to form adduct with metal compounds. The instant disclosure also includes an assembly for carrying out the recovery and regeneration of the ionic liquids.
    Type: Application
    Filed: July 8, 2015
    Publication date: July 13, 2017
    Inventors: Akhilesh YADAV, Parasuveera UPPARA, Pavan Kumar ADURI, Viswanath KOTRA, Vibhuti DUKHANDE