Abstract: In certain aspects, a chip includes first source/drain contacts formed over a first oxide diffusion (OD), and first gates, wherein each of the first gates is disposed between a respective pair of the first source/drain contacts. The chip also includes a first bridge coupling a first one of the first source/drain contacts, a first one of the first gates, and a second one of the first source/drain contacts. The chip also includes a first metal routing coupled to the first one of the first source/drain contacts, and a second metal routing coupled to the second one of the first source/drain contacts.

Abstract: According to certain aspects, a level shifter includes a first branch including a first pull-up transistor configured to pull up a first node, and a first pull-down transistor configured to pull down the first node. The level shifter also includes a second branch including a second pull-up transistor configured to pull up a second node, and a second pull-down transistor configured to pull down the second node. The level shifter further includes a third branch including a third pull-up transistor configured to pull up a third node, and a third pull-down transistor configured to pull down the third node. The first branch is cross coupled with the third branch, the second branch is cross coupled with the third branch, the first pull-down transistor has a first channel width, the second pull-down transistor has a second channel width, and the first channel width is greater than the second channel width.

Abstract: According to certain aspects, a level shifter includes a first branch including a first pull-up transistor configured to pull up a first node, and a first pull-down transistor configured to pull down the first node. The level shifter also includes a second branch including a second pull-up transistor configured to pull up a second node, and a second pull-down transistor configured to pull down the second node. The level shifter further includes a third branch including a third pull-up transistor configured to pull up a third node, and a third pull-down transistor configured to pull down the third node. The first branch is cross coupled with the third branch, the second branch is cross coupled with the third branch, the first pull-down transistor has a first channel width, the second pull-down transistor has a second channel width, and the first channel width is greater than the second channel width.

Abstract: A method and system for optimizing an integrated circuit is described. The method includes generating (102) a characteristic table of the integrated circuit. The method further includes selecting (104) a functional module from one or more functional modules. Moreover, the method includes receiving (106) at least an input load or an output load, or both, corresponding to the functional module. Further still, the method includes calculating (108) size of a plurality of transistors in the functional module. The system includes a characteristic table generator (302) and an optimizer unit (304). The characteristic table generator (302) generates the characteristic table. The optimizer unit (304) selects the functional module from the one or more functional modules. The optimizer unit (302) further resizes the plurality of transistors in the functional module.

Abstract: A method and system for optimizing an integrated circuit is described. The method includes generating (102) a characteristic table of the integrated circuit. The method further includes selecting (104) a functional module from one or more functional modules. Moreover, the method includes receiving (106) at least an input load or an output load, or both, corresponding to the functional module. Further still, the method includes calculating (108) size of a plurality of transistors in the functional module. The system includes a characteristic table generator (302) and an optimizer unit (304). The characteristic table generator (302) generates the characteristic table. The optimizer unit (304) selects the functional module from the one or more functional modules. The optimizer unit (302) further resizes the plurality of transistors in the functional module.