Abstract: Apparatus for converting a first input signal from a first voltage domain to an output signal for a second voltage domain, the apparatus configured to operate within the first voltage domain or within the second voltage domain. The apparatus comprising input driver circuitry configured to generate second input signal based on the first input signal and a control signal received by input driver circuitry. The apparatus also comprising selection circuitry configured to generate a selection signal based on the control signal. The apparatus also comprising cross-coupled circuitry configured to generate a level-shifted signal at an intermediate node based on the first input signal, the second input signal, and the selection signal. The cross-coupled circuitry comprises a first pair of parallel transistors and a second pair of parallel transistors. The apparatus further comprising output driver circuitry configured to generate output signal for the second voltage domain based on the level-shifted signal.

Abstract: A data storage circuit for receiving and holding a data value includes an input stage configured to receive a data value in response to the precharge phase changing to an evaluation phase and to hold the data value during the evaluation phase. An output stage has an output latching element for holding the value, two switching devices for updating the output latching element and an output. The switching devices each being controlled by respective signals from dual data lines, wherein, in response to the data value held in the input stage being a logical one, the first switching device updates the output latching element with a value indicative of the logical one and in response to the data value held in the input stage being a logical zero, the second switching device updates the output latching element with a value indicative of the logical zero.

Abstract: A data storage circuit for receiving and holding a data value includes an input stage configured to receive a data value in response to the precharge phase changing to an evaluation phase and to hold the data value during the evaluation phase. An output stage has an output latching element for holding the value, two switching devices for updating the output latching element and an output. The switching devices each being controlled by respective signals from dual data lines, wherein, in response to the data value held in the input stage being a logical one, the first switching device updates the output latching element with a value indicative of the logical one and in response to the data value held in the input stage being a logical zero, the second switching device updates the output latching element with a value indicative of the logical zero.