Patents by Inventor Aki Fujimura

Aki Fujimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230153610
    Abstract: Some embodiments provide a method of training a neural network to identify a type of golf swing based on a sound produced by an impact between a clubhead of a golf club and a golf ball. The method provides the neural network with multiple sets of inputs associated with multiple swings and multiple corresponding sets of known outputs. Each set of inputs includes at least (1) a spectrogram associated with sounds produced by the swing, and (2) impact position derived from impact tape on the clubhead used during the swing. The method uses the neural network to process each set of inputs to produce multiple sets of generated outputs. The method compares the known outputs with the generated outputs to compute error values that express differences between the known and generated outputs. The method propagates inputs associated with the computed error values back through the neural network and adjusts one or more adjustable parameters based on the computed error values.
    Type: Application
    Filed: November 17, 2022
    Publication date: May 18, 2023
    Inventors: Emi Siao Fujimura, Tadashi Siao Fujimura, Aki Fujimura, Tanish Baranwal
  • Patent number: 7089516
    Abstract: The present invention relates to techniques for measuring integrated circuit interconnect process parameters. The techniques are applicable to any non-ideally shaped interconnects made from any type of conductive materials. Test structures are fabricated within an integrated circuit. Non-destructive electrical measurements are taken from the test structures to determine coupling capacitances associated with the test structures. A field solver uses the initial process parameters to determine design coupling capacitances. An optimizer then uses the measured coupling capacitances and the design coupling capacitances to determine the interconnect process parameters.
    Type: Grant
    Filed: March 22, 2004
    Date of Patent: August 8, 2006
    Assignee: Cadence Design Systems, Inc.
    Inventors: Narain D. Arora, Li J. Song, Aki Fujimura
  • Patent number: 7024638
    Abstract: To increase the writing speed of masks, context information can be used to distinguish the attributes of portions of the mask that are critical from attributes, and portions, that are less critical. By using this information, which may be derived from the design context of the features, the mask can be written at a higher speed without sacrificing the accuracy of the important attributes or features.
    Type: Grant
    Filed: July 14, 2003
    Date of Patent: April 4, 2006
    Assignee: Cadence Design Systems, Inc.
    Inventors: Louis K. Scheffer, Kenji Yoshida, Yoshikuni Abe, Aki Fujimura, Robert C. Pack
  • Publication number: 20050206394
    Abstract: The present invention relates to techniques for measuring integrated circuit interconnect process parameters. The techniques are applicable to any non-ideally shaped interconnects made from any type of conductive materials. Test structures are fabricated within an integrated circuit. Non-destructive electrical measurements are taken from the test structures to determine coupling capacitances associated with the test structures. A field solver uses the initial process parameters to determine design coupling capacitances. An optimizer then uses the measured coupling capacitances and the design coupling capacitances to determine the interconnect process parameters.
    Type: Application
    Filed: March 22, 2004
    Publication date: September 22, 2005
    Inventors: Narain Arora, Li Song, Aki Fujimura
  • Publication number: 20050015739
    Abstract: To increase the writing speed of masks, context information can be used to distinguish the attributes of portions of the mask that are critical from attributes, and portions, that are less critical. By using this information, which may be derived from the design context of the features, the mask can be written at a higher speed without sacrificing the accuracy of the important attributes or features.
    Type: Application
    Filed: July 14, 2003
    Publication date: January 20, 2005
    Applicant: Cadence Design Systems, Inc.
    Inventors: Louis Scheffer, Kenji Yoshida, Yoshikuni Abe, Aki Fujimura, Robert Pack