Patents by Inventor Aki Niimura
Aki Niimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8738856Abstract: A system and methods are shown for handling multiple target memory requests. Memory read requests generated by a peripheral component interconnect (PCI) client are received by a PCI bus controller. The PCI bus controller passes the memory request to a memory controller used to access main memory. The memory controller passes the memory request to a bus interface unit used to access cache memory and a processor. The bus interface unit determines if cache memory can be used to provide the data associated with the PCI client's memory request. While the bus interface unit determines if cache memory may be used, the memory controller continues to process the memory request to main memory. If cache memory can be used, the bus interface unit provides the data to the PCI client and sends a notification to the memory controller.Type: GrantFiled: April 24, 2007Date of Patent: May 27, 2014Assignee: ATI Technologies, Inc.Inventors: Michael Frank, Santiago Fernandez-Gomez, Robert W. Laker, Aki Niimura
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Patent number: 8452910Abstract: Split capture of USB protocol streams is disclosed. A first set of packets associated with a first USB protocol and a second set of packets associated with a second USB protocol are received at a hardware protocol analyzer via a monitored bus. The first set of packets and the second set of packets are maintained as separate streams at the hardware protocol analyzer. The first set of packets and the second set of packets are transferred from the hardware protocol analyzer to an analysis computer via a first logical connection configured to transfer packets comprising the first set of packets and a second logical connection configured to transfer packets comprising the second set of packets.Type: GrantFiled: October 21, 2010Date of Patent: May 28, 2013Assignee: Total Phase, Inc.Inventors: Etai Bruhis, Gopal Santhanam, Aki Niimura
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Patent number: 8443222Abstract: VBUS or other power event based USB analysis is disclosed. Occurrence of a power related event on a monitored bus, such as an inrush current event, is detected. In some embodiments, a rate at which a power related data is sampled at the hardware protocol analyzer is change automatically in response to the power related event being detected. In some embodiments, a capture of a stream of data packets observed on the monitored bus is triggering automatically in response to the power related event being detected.Type: GrantFiled: October 21, 2010Date of Patent: May 14, 2013Assignee: Total Phase, Inc.Inventor: Aki Niimura
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Publication number: 20070255904Abstract: A system and methods are shown for handling multiple target memory requests. Memory read requests generated by a peripheral component interconnect (PCI) client are received by a PCI bus controller. The PCI bus controller passes the memory request to a memory controller used to access main memory. The memory controller passes the memory request to a bus interface unit used to access cache memory and a processor. The bus interface unit determines if cache memory can be used to provide the data associated with the PCI client's memory request. While the bus interface unit determines if cache memory may be used, the memory controller continues to process the memory request to main memory. If cache memory can be used, the bus interface unit provides the data to the PCI client and sends a notification to the memory controller.Type: ApplicationFiled: April 24, 2007Publication date: November 1, 2007Applicant: ATI TECHNOLOGIES, INC.Inventors: Michael Frank, Santiago Fernandez-Gomez, Robert Laker, Aki Niimura
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Patent number: 7240157Abstract: A system and methods are shown for handling multiple target memory requests. Memory read requests generated by a peripheral component interconnect (PCI) client are received by a PCI bus controller. The PCI bus controller passes the memory request to a memory controller used to access main memory. The memory controller passes the memory request to a bus interface unit used to access cache memory and a processor. The bus interface unit determines if cache memory can be used to provide the data associated with the PCI client's memory request. While the bus interface unit determines if cache memory may be used, the memory controller continues to process the memory request to main memory. If cache memory can be used, the bus interface unit provides the data to the PCI client and sends a notification to the memory controller.Type: GrantFiled: September 26, 2001Date of Patent: July 3, 2007Assignee: ATI Technologies, Inc.Inventors: Michael Frank, Santiago Fernandez-Gomez, Robert W. Laker, Aki Niimura
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Patent number: 6745308Abstract: A method and system are shown for bypassing memory controller components when processing memory requests. A memory controller analyzes internal components to determine if any pending memory requests exist. If particular memory controller components are idle, a memory client is informed that a bypassing of memory controller components is possible. A bypass module of the memory controller receives memory requests from the memory client. The bypass module examines memory controller parameters and a configuration of main memory to determine which memory controller components may be bypassed and routes the memory request accordingly. In a system with asynchronous memory, the memory controller provides copies of the memory request through a dual pipeline. A first copy of the memory request is processed through a bypass module to attempt to bypass memory controller components. A second copy of the memory request is processed in a normal fashion in case a bypass of the memory access request is not possible.Type: GrantFiled: February 19, 2002Date of Patent: June 1, 2004Assignee: ATI Technologies, Inc.Inventors: Michael Frank, Santiago Fernandez-Gomez, Robert W. Laker, Aki Niimura
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Publication number: 20030159013Abstract: A method and system are shown for bypassing memory controller components when processing memory requests. A memory controller analyzes internal components to determine if any pending memory requests exist. If particular memory controller components are idle, a memory client is informed that a bypassing of memory controller components is possible. A bypass module of the memory controller receives memory requests from the memory client. The bypass module examines memory controller parameters and a configuration of main memory to determine which memory controller components may be bypassed and routes the memory request accordingly. In a system with asynchronous memory, the memory controller provides copies of the memory request through a dual pipeline. A first copy of the memory request is processed through a bypass module to attempt to bypass memory controller components. A second copy of the memory request is processed in a normal fashion in case a bypass of the memory access request is not possible.Type: ApplicationFiled: February 19, 2002Publication date: August 21, 2003Inventors: Michael Frank, Santiago Fernandez-Gomez, Robert W. Laker, Aki Niimura
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Publication number: 20030061443Abstract: A system and methods are shown for handling multiple target memory requests. Memory read requests generated by a peripheral component interconnect (PCI) client are received by a PCI bus controller. The PCI bus controller passes the memory request to a memory controller used to access main memory. The memory controller passes the memory request to a bus interface unit used to access cache memory and a processor. The bus interface unit determines if cache memory can be used to provide the data associated with the PCI client's memory request. While the bus interface unit determines if cache memory may be used, the memory controller continues to process the memory request to main memory. If cache memory can be used, the bus interface unit provides the data to the PCI client and sends a notification to the memory controller.Type: ApplicationFiled: September 26, 2001Publication date: March 27, 2003Inventors: Michael Frank, Santiago Fernandez-Gomez, Robert W. Laker, Aki Niimura