Abstract: The silicon carbide semiconductor device includes: a silicon carbide layer; a silicon dioxide layer provided above the silicon carbide layer and containing nitrogen; and a transition region arranged between the silicon carbide layer and the silicon dioxide layer, and containing carbon, oxygen, and nitrogen, wherein the maximum nitrogen concentration in the transition region is 1.0×1020 cm?3 or higher. The maximum nitrogen concentration in the transition region is five or more times higher than the maximum nitrogen concentration in the silicon dioxide layer.

Abstract: After trench etching, trench corner portions are rounded by hydrogen annealing at a temperature of at least 1500 degrees C. Next, n-type regions that cause leak current and are formed in inner walls of the trenches by the hydrogen annealing are removed by a heat treatment (hydrogen etching) under a hydrogen atmosphere of a temperature less than 1500 degrees C. and the inner walls are planarized. Next, the inner walls are nitrided by introducing nitrogen into the heat treatment furnace while the temperature of the hydrogen-etching heat treatment decreases, thereby forming a SiN film along the inner walls. Next, an HTO film is formed, as gate insulating films, on the SiN film along the inner walls of the trenches. Thereafter, by PDA, an oxygen amount of an interface section of a SiO2/SiC interface is set to be at most 1.6×1015/cm2 and a nitrogen amount is set to more than 5.0×1014/cm2.

Abstract: The silicon carbide semiconductor device includes: a silicon carbide layer; a silicon dioxide layer provided above the silicon carbide layer and containing nitrogen; and a transition region arranged between the silicon carbide layer and the silicon dioxide layer, and containing carbon, oxygen, and nitrogen, wherein the maximum nitrogen concentration in the transition region is 1.0×1020 cm?3 or higher. The maximum nitrogen concentration in the transition region is five or more times higher than the maximum nitrogen concentration in the silicon dioxide layer.

Abstract: A semiconductor device including a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, provided at a front surface of the semiconductor substrate and having an impurity concentration lower than that of the semiconductor substrate, a second semiconductor layer of a second conductivity type, selectively provided on the first semiconductor layer, a first semiconductor region of the first conductivity type, selectively provided in the second semiconductor layer and having an impurity concentration higher than that of the semiconductor substrate, a trench penetrating the first semiconductor region and the second semiconductor layer, to reach the first semiconductor layer, and a gate electrode provided in the trench, via a gate insulating film. The trench has a sidewall that includes a terrace portion, surface roughness of the terrace portion being at most 0.1 nm.

Abstract: After trench etching, trench corner portions are rounded by hydrogen annealing at a temperature of at least 1500 degrees C. Next, n-type regions that cause leak current and are formed in inner walls of the trenches by the hydrogen annealing are removed by a heat treatment (hydrogen etching) under a hydrogen atmosphere of a temperature less than 1500 degrees C. and the inner walls are planarized. Next, the inner walls are nitrided by introducing nitrogen into the heat treatment furnace while the temperature of the hydrogen-etching heat treatment decreases, thereby forming a SiN film along the inner walls. Next, an HTO film is formed, as gate insulating films, on the SiN film along the inner walls of the trenches. Thereafter, by PDA, an oxygen amount of an interface section of a SiO2/SiC interface is set to be at most 1.6×1015/cm2 and a nitrogen amount is set to more than 5.0×1014/cm2.

Abstract: A semiconductor device including a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, provided at a front surface of the semiconductor substrate and having an impurity concentration lower than that of the semiconductor substrate, a second semiconductor layer of a second conductivity type, selectively provided on the first semiconductor layer, a first semiconductor region of the first conductivity type, selectively provided in the second semiconductor layer and having an impurity concentration higher than that of the semiconductor substrate, a trench penetrating the first semiconductor region and the second semiconductor layer, to reach the first semiconductor layer, and a gate electrode provided in the trench, via a gate insulating film. The trench has a sidewall that includes a terrace portion, surface roughness of the terrace portion being at most 0.1 nm.

Abstract: A method of evaluating an insulated-gate semiconductor device having an insulated-gate structure including a channel formation layer made of a wide-bandgap semiconductor and a gate insulating film formed contacting the channel formation layer includes removing the gate insulating film in order to expose a surface of the channel formation layer; taking a phase image of the exposed surface of the channel formation layer using a phase mode of an atomic force microscope; evaluating a surface condition of the exposed surface of the channel formation layer by calculating an evaluation metric from phase shift values in the phase image and by determining whether the evaluation metric satisfies a prescribed condition; and determining that the insulated-gate semiconductor device is acceptable when the evaluation metric satisfied the prescribed condition.

Abstract: A method of evaluating an insulated-gate semiconductor device having an insulated-gate structure including a channel formation layer made of a wide-bandgap semiconductor and a gate insulating film formed contacting the channel formation layer includes removing the gate insulating film in order to expose a surface of the channel formation layer; taking a phase image of the exposed surface of the channel formation layer using a phase mode of an atomic force microscope; evaluating a surface condition of the exposed surface of the channel formation layer by calculating an evaluation metric from phase shift values in the phase image and by determining whether the evaluation metric satisfies a prescribed condition; and determining that the insulated-gate semiconductor device is acceptable when the evaluation metric satisfied the prescribed condition.

Abstract: Provided is a MOS gate using a thermally oxidized film as a gate insulating film on the front surface of a silicon carbide substrate. A ratio of an excess carbon amount at an SiO2/SiC interface in relation to a carbon amount in the silicon carbide substrate is 0.1 or less. The excess carbon at the SiO2/SiC interface is generated during thermal oxidation for forming the gate insulating film. The excess carbon is a compound constituted of carbon atoms having the pi (it) bonds, and specifically is graphite, for example. The amount of nitrogen at the SiO2/SiC interface is 1.4×1015/cm2 to 1.8×1015/cm2, inclusive, for example.