Abstract: One embodiment provides for a processor comprising a three-dimensional (3D) integrated circuit stack including multiple graphics processor cores and interconnect logic to interconnect the graphics processor cores of the 3D integrated circuit stack to enable data distribution between the graphics processor cores over a virtual channel including multiple programmatically pre-assigned traffic classifications.

Abstract: One embodiment provides for a processor comprising a three-dimensional (3D) integrated circuit stack including multiple graphics processor cores and interconnect logic to interconnect the graphics processor cores of the 3D integrated circuit stack to enable data distribution between the graphics processor cores over a virtual channel including multiple programmatically pre-assigned traffic classifications.

Abstract: In on embodiment, a hybrid fabric interconnects multiple graphics processor cores within a processor. The hybrid fabric interconnect includes multiple data channels, including programmable virtual data channels. The virtual data channels carry multiple traffic classes of packet-based messages. The virtual data channels and multiple traffic classes may be assigned one of multiple priorities. The virtual data channels may be arbitrated independently. The hybrid fabric is scalable and can support multiple topologies, including multiple stacked integrated circuit topologies.

Abstract: In on embodiment, a hybrid fabric interconnects multiple graphics processor cores within a processor. The hybrid fabric interconnect includes multiple data channels, including programmable virtual data channels. The virtual data channels carry multiple traffic classes of packet-based messages. The virtual data channels and multiple traffic classes may be assigned one of multiple priorities. The virtual data channels may be arbitrated independently. The hybrid fabric is scalable and can support multiple topologies, including multiple stacked integrated circuit topologies.

Abstract: In on embodiment, a hybrid fabric interconnects multiple graphics processor cores within a processor. The hybrid fabric interconnect includes multiple data channels, including programmable virtual data channels. The virtual data channels carry multiple traffic classes of packet-based messages. The virtual data channels and multiple traffic classes may be assigned one of multiple priorities. The virtual data channels may be arbitrated independently. The hybrid fabric is scalable and can support multiple topologies, including multiple stacked integrated circuit topologies.

Abstract: In on embodiment, a hybrid fabric interconnects multiple graphics processor cores within a processor. The hybrid fabric interconnect includes multiple data channels, including programmable virtual data channels. The virtual data channels carry multiple traffic classes of packet-based messages. The virtual data channels and multiple traffic classes may be assigned one of multiple priorities. The virtual data channels may be arbitrated independently. The hybrid fabric is scalable and can support multiple topologies, including multiple stacked integrated circuit topologies.

Abstract: In on embodiment, a hybrid fabric interconnects multiple graphics processor cores within a processor. The hybrid fabric interconnect includes multiple data channels, including programmable virtual data channels. The virtual data channels carry multiple traffic classes of packet-based messages. The virtual data channels and multiple traffic classes may be assigned one of multiple priorities. The virtual data channels may be arbitrated independently. The hybrid fabric is scalable and can support multiple topologies, including multiple stacked integrated circuit topologies.

Abstract: A circuit for identifying one or more bit positions of instances of a selected bit value in an N-bit input bit string includes a plurality of adders that compute, in parallel, sums of bits in each of P input substrings comprising the input bit string. A plurality of zero position detectors detect, for each of the P input substrings for which a corresponding sum differs from a threshold sum, one or more bit positions of the selected bit value. Correction logic generates adjustment indications indicative of a number of detected instances of the selected bit value. A plurality of output substring adjusters that, based on the detected bit positions and the adjustment indications, collectively output one or more output vectors identifying a bit position of at least an Mth instance of the selected bit value in the input bit string.

Abstract: In on embodiment, a hybrid fabric interconnects multiple graphics processor cores within a processor. The hybrid fabric interconnect includes multiple data channels, including programmable virtual data channels. The virtual data channels carry multiple traffic classes of packet-based messages. The virtual data channels and multiple traffic classes may be assigned one of multiple priorities. The virtual data channels may be arbitrated independently. The hybrid fabric is scalable and can support multiple topologies, including multiple stacked integrated circuit topologies.

Abstract: A circuit for identifying one or more bit positions of instances of a selected bit value in an N-bit input bit string includes a plurality of adders that compute, in parallel, sums of bits in each of P input substrings comprising the input bit string. A plurality of zero position detectors detect, for each of the P input substrings for which a corresponding sum differs from a threshold sum, one or more bit positions of the selected bit value. Correction logic generates adjustment indications indicative of a number of detected instances of the selected bit value. A plurality of output substring adjusters that, based on the detected bit positions and the adjustment indications, collectively output one or more output vectors identifying a bit position of at least an Mth instance of the selected bit value in the input bit string.