Abstract: A circuit for identifying one or more bit positions of instances of a selected bit value in an N-bit input bit string includes a plurality of adders that compute, in parallel, sums of bits in each of P input substrings comprising the input bit string. A plurality of zero position detectors detect, for each of the P input substrings for which a corresponding sum differs from a threshold sum, one or more bit positions of the selected bit value. Correction logic generates adjustment indications indicative of a number of detected instances of the selected bit value. A plurality of output substring adjusters that, based on the detected bit positions and the adjustment indications, collectively output one or more output vectors identifying a bit position of at least an Mth instance of the selected bit value in the input bit string.

Abstract: A circuit for identifying one or more bit positions of instances of a selected bit value in an N-bit input bit string includes a plurality of adders that compute, in parallel, sums of bits in each of P input substrings comprising the input bit string. A plurality of zero position detectors detect, for each of the P input substrings for which a corresponding sum differs from a threshold sum, one or more bit positions of the selected bit value. Correction logic generates adjustment indications indicative of a number of detected instances of the selected bit value. A plurality of output substring adjusters that, based on the detected bit positions and the adjustment indications, collectively output one or more output vectors identifying a bit position of at least an Mth instance of the selected bit value in the input bit string.