Patents by Inventor Akifumi Imai
Akifumi Imai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12142675Abstract: The present invention relates to a heterojunction field effect transistor, and the heterojunction field effect transistor includes a barrier layer provided in an upper layer portion of a channel layer of a first nitride semiconductor, being formed of a second nitride semiconductor hetero-joined to the first nitride semiconductor, first and second impurity regions provided, being spaced each other with the barrier layer interposed therebetween, a source electrode and a drain electrode which are provided on the first and second impurity regions, respectively, an insulating film which is so provided as to come into contact with at least a region of the barrier layer excluding an edge portion thereof on the side of the source electrode, a gate insulating film which is in contact with the edge portion of the barrier layer and covers the insulating film, and a gate electrode which is so provided on the gate insulating film.Type: GrantFiled: November 11, 2019Date of Patent: November 12, 2024Assignee: MITSUBISHI ELECTRIC CORPORATIONInventors: Takuma Nanjo, Akifumi Imai, Tatsuro Watahiki
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Publication number: 20220199821Abstract: The present invention relates to a heterojunction field effect transistor, and the heterojunction field effect transistor includes a barrier layer provided in an upper layer portion of a channel layer of a first nitride semiconductor, being formed of a second nitride semiconductor hetero-joined to the first nitride semiconductor, first and second impurity regions provided, being spaced each other with the barrier layer interposed therebetween, a source electrode and a drain electrode which are provided on the first and second impurity regions, respectively, an insulating film which is so provided as to come into contact with at least a region of the barrier layer excluding an edge portion thereof on the side of the source electrode, a gate insulating film which is in contact with the edge portion of the barrier layer and covers the insulating film, and a gate electrode which is so provided on the gate insulating film.Type: ApplicationFiled: November 11, 2019Publication date: June 23, 2022Applicant: Mitsubishi Electric CorporationInventors: Takuma NANJO, Akifumi IMAI, Tatsuro WATAHIKI
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Patent number: 11107685Abstract: The semiconductor manufacturing device includes: a lower substrate support base configured to support a diamond substrate; an upper substrate support base configured to support a semiconductor substrate; a support base drive unit configured to move the lower substrate support base and the upper substrate support base to bring the diamond substrate and the semiconductor substrate into close contact with each other under a state in which a pressure is applied to the diamond substrate and the semiconductor substrate in a thickness direction; and a second mechanism configured to deform a surface of the upper substrate support base opposed to the lower substrate support base so that a surface of the semiconductor substrate opposed to the diamond substrate forms a parallel surface or a parallel plane with respect to a surface of the diamond substrate opposed to the semiconductor substrate.Type: GrantFiled: February 1, 2018Date of Patent: August 31, 2021Assignee: MITSUBISHI ELECTRIC CORPORATIONInventors: Keisuke Nakamura, Muneyoshi Suita, Akifumi Imai, Kenichiro Kurahashi, Tomohiro Shinagawa, Takashi Matsuda, Koji Yoshitsugu, Eiji Yagyu, Kunihiko Nishimura
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Publication number: 20190362974Abstract: The semiconductor manufacturing device includes: a lower substrate support base configured to support a diamond substrate; an upper substrate support base configured to support a semiconductor substrate; a support base drive unit configured to move the lower substrate support base and the upper substrate support base to bring the diamond substrate and the semiconductor substrate into close contact with each other under a state in which a pressure is applied to the diamond substrate and the semiconductor substrate in a thickness direction; and a second mechanism configured to deform a surface of the upper substrate support base opposed to the lower substrate support base so that a surface of the semiconductor substrate opposed to the diamond substrate forms a parallel surface or a parallel plane with respect to a surface of the diamond substrate opposed to the semiconductor substrate.Type: ApplicationFiled: February 1, 2018Publication date: November 28, 2019Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Keisuke NAKAMURA, Muneyoshi SUITA, Akifumi IMAI, Kenichiro KURAHASHI, Tomohiro SHINAGAWA, Takashi MATSUDA, Koji YOSHITSUGU, Eiji YAGYU, Kunihiko NISHIMURA
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Patent number: 9893210Abstract: A semiconductor device includes: a substrate; a nitride semiconductor layer on the substrate; a source electrode, a drain electrode and a gate electrode on the nitride semiconductor layer; and a SiN surface protective film covering the nitride semiconductor layer, wherein a composition ratio Si/N of Si and N that form a Si—N bond of the SiN surface protective film is 0.751 to 0.801.Type: GrantFiled: June 6, 2016Date of Patent: February 13, 2018Assignee: Mitsubishi Electric CorporationInventors: Kenichiro Kurahashi, Takuma Nanjo, Muneyoshi Suita, Akifumi Imai, Eiji Yagyu, Hiroyuki Okazaki
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Publication number: 20170092783Abstract: A semiconductor device includes: a substrate; a nitride semiconductor layer on the substrate; a source electrode, a drain electrode and a gate electrode on the nitride semiconductor layer; and a SiN surface protective film covering the nitride semiconductor layer, wherein a composition ratio Si/N of Si and N that form a Si—N bond of the SiN surface protective film is 0.751 to 0.Type: ApplicationFiled: June 6, 2016Publication date: March 30, 2017Applicant: Mitsubishi Electric CorporationInventors: Kenichiro KURAHASHI, Takuma NANJO, Muneyoshi SUITA, Akifumi IMAI, Eiji YAGYU, Hiroyuki OKAZAKI
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Publication number: 20150228756Abstract: A semiconductor device includes an Alx1Ga1-x1N (0?x1?1) barrier layer, and a gate electrode that is disposed on a surface of the Alx1Ga1-x1N (0?x1?1) barrier layer, forms a Schottky junction with the surface of the Alx1Ga1-x1N (0?x1?1) barrier layer, and has an Ni single-layer structure. Annealing processing is performed with respect to the gate electrode at a temperature of 500° C. or above under a nitrogen atmosphere to form a reaction layer between the surface of the Alx1Ga1-x1N (0?x1?1) barrier layer and the gate electrode.Type: ApplicationFiled: February 2, 2015Publication date: August 13, 2015Applicant: Mitsubishi Electric CorporationInventors: Kenichiro KURAHASHI, Takuma Nanjo, Muneyoshi Suita, Yosuke Suzuki, Akifumi Imai, Marika Nakamura, Eiji Yagyu
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Patent number: 8987125Abstract: The present invention relates to a method for manufacturing a heterojunction semiconductor device including an AlGaN layer, the method including the steps of (a) forming a dummy electrode in a region where a gate electrode is arranged on the AlGaN layer, (b) depositing a dielectric film on the AlGaN layer by exposing side surfaces of the dummy electrode, using a device having anisotropy, (c) forming an opening in the dielectric film by removing the dummy electrode, and (d) forming the gate electrode that extends from inside the opening onto the dielectric film in a vicinity of the opening.Type: GrantFiled: June 5, 2013Date of Patent: March 24, 2015Assignee: Mitsubishi Electric CorporationInventors: Hiroyuki Okazaki, Takuma Nanjo, Yosuke Suzuki, Akifumi Imai, Muneyoshi Suita, Eiji Yagyu
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Publication number: 20150069408Abstract: A laminate includes a surface on which a gate electrode is provided, and is made of a nitride semiconductor. The laminate includes a first layer having a first band gap, and a second layer provided between the first layer and the surface and having a second band gap which is larger than the first band gap. The first and second layers and form a joint surface by a hetero junction. The surface includes a surface defect density equal to or smaller than 1.7×106 cm?2.Type: ApplicationFiled: August 28, 2014Publication date: March 12, 2015Applicant: Mitsubishi Electric CorporationInventors: Takuma NANJO, Akifumi IMAI, Yosuke SUZUKI, Muneyoshi SUITA, Kenichiro KURAHASHI, Marika NAKAMURA, Eiji YAGYU
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Publication number: 20140011349Abstract: The present invention relates to a method for manufacturing a heterojunction semiconductor device including an AlGaN layer, the method including the steps of (a) forming a dummy electrode in a region where a gate electrode is arranged on the AlGaN layer, (b) depositing a dielectric film on the AlGaN layer by exposing side surfaces of the dummy electrode, using a device having anisotropy, (c) forming an opening in the dielectric film by removing the dummy electrode, and (d) forming the gate electrode that extends from inside the opening onto the dielectric film in a vicinity of the opening.Type: ApplicationFiled: June 5, 2013Publication date: January 9, 2014Inventors: Hiroyuki OKAZAKI, Takuma Nanjo, Yosuke Suzuki, Akifumi Imai, Muneyoshi Suita, Eiji Yagyu