Abstract: According to the present invention, an imaging unit, comprising an imaging device, an imaging device driver, and a signal-processing block, is provided. The imaging device has pixels which are arranged in a first direction. The pixels are alternately and repeatedly covered with N1 kinds of different color filters along the first direction. The imaging device driver drives the imaging device. N1*N2 pixels successively arranged in the first direction are defined as a pixel block. The imaging device driver orders the N1 pixels covered with the different color filters in the pixel block to output pixel signals when a first output method with thinning out is carried out.

Abstract: An imaging device driver that drives an imaging device, comprising a controller, is provided. The imaging device has the light receiving surface divided into a plurality of pixel blocks. Each pixel block has a plurality of pixels. The pixel generates a pixel signal according to received light amount. The imaging device generates an image signal. The image signal is formed by a plurality of the pixel signals. The image signal corresponds to an optical image of an object during a single frame period. The controller causes the pixel located at a first and a second area in the pixel block to generate the pixel signal in a first and a second frame period, respectively, if the imaging device is driven to output the image signal while thinning out the pixel signals. The second frame period follows the first frame period.

Abstract: An endoscope control unit including an imaging device controller and a first signal-processing circuit, is provided. The endoscope control unit orders a CMOS imaging device to capture an image and to carry out signal processing for supplying an image signal to a monitor. The CMOS imaging device generates the image signal on the basis of the captured image. The imaging device controller orders the CMOS imaging device to generate a frame's worth of image signal every first period. The first period is shorter than a second period. The image to be displayed on the monitor is refreshed every second period in order to displaying a moving image. The first signal-processing circuit outputs one frame of the image signal generated by the CMOS imaging device to the monitor every second period.

Abstract: According to the present invention, an imaging unit, comprising an imaging device, an imaging device driver, and a signal-processing block, is provided. The imaging device has pixels which are arranged in a first direction. The pixels are alternately and repeatedly covered with N1 kinds of different color filters along the first direction. The imaging device driver drives the imaging device. N1*N2 pixels successively arranged in the first direction are defined as a pixel block. The imaging device driver orders the N1 pixels covered with the different color filters in the pixel block to output pixel signals when a first output method with thinning out is carried out.

Abstract: An imaging device driver that drives an imaging device, comprising a controller, is provided. The imaging device has the light receiving surface divided into a plurality of pixel blocks. Each pixel block has a plurality of pixels. The pixel generates a pixel signal according to received light amount. The imaging device generates an image signal. The image signal is formed by a plurality of the pixel signals. The image signal corresponds to an optical image of an object during a single frame period. The controller causes the pixel located at a first and a second area in the pixel block to generate the pixel signal in a first and a second frame period, respectively, if the imaging device is driven to output the image signal while thinning out the pixel signals. The second frame period follows the first frame period.

Abstract: The present invention relates to a video signal processing apparatus for outputting an inputted video signal after subjecting the video signal to time axis correction, particularly to a video signal processing apparatus preferable in the case of subjecting the video signal to image compression. In the case in which a nonstandard signal is inputted to an image compression circuit of an MPEG2 encoder or the like, a drawback of freezing image or generating block noise or the like is resolved. A time axis correcting circuit stores an input signal to a memory and reads the input signal at a timing delayed from V synchronization of the input signal by a predetermined time period. For that purpose, a read synchronizing signal generator is reset at respective input field. A reset position is set to a position preceding the read V synchronization position by 3H through 10H.

Abstract: A video signal processing apparatus includes an equalizer for delaying an input color signal by an adjustable phase retardation. A low pass filter is operative for delaying the input color signal by an adjustable phase retardation. A phase detector is operative for detecting a difference between a phase of an output signal of the equalizer and a phase of an output signal of the low pass filter, and outputting a signal representative of the detected phase difference. The phase retardation provided by the equalizer and the phase retardation provided by the low pass filter are adjusted in response to the output signal of the phase detector to maintain the difference between the phase of the output signal of the equalizer and the phase of the output signal of the low pass filter at a predetermined value, for example, 90 degrees.