Abstract: A method and apparatus for merging a plurality of input data strings employ a unit to execute a vector processing for two-way merging to carry out merging iteratively, while setting the number of vector elements for the merging unit for the input data strings, deliver the result of merging, and, when a certain number of vacant areas become available in a input data area, load the certain number of data of the associated input data string to the vacant areas. Delivery of the merged result and loading of an input data string to the input data area take place in parallel.

Abstract: A vector processor includes a memory for storing vector data, a processing circuit, a fetch circuit for sequentially fetching elements of a first vector data to be processed from the memory and supplying them to the processing circuit, a generation circuit for generating tag information to designate the fetched vector elements, and a write circuit responsive to the process result by the processing means for writing the tag information generated for the element having a predetermined process result into the memory as one element of a second vector data.

Abstract: A vector processing system including a main storage for storing vector instructions and vector data, an instruction register for holding a vector instruction read out of the main storage, a decoder for decoding the vector instruction held in the instruction register, and an execution unit, operative to implement a vector operation in response to an output of the decoder, including a facility which, when a sort instruction inclusive of a vector starting address, increment switching parameter and an operation switching parameter has been set up in the instruction register, implements a sorting process specified by the instruction for vector data stored in the main storage, the facility including a circuit in which the operation switching parameter is set and which produces an operation switching signal in compliance with the number of operations and the position of a vector element to be operated, a circuit in which the increment switching parameter is set and which produces an increment switching signal in com