Patents by Inventor Akihide TAKAHASHI

Akihide TAKAHASHI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10766405
    Abstract: To provide a semiconductor device which suppresses a message image projected by a mobile from varying from a desired position. A semiconductor device has a first area decision part which decides a first area onto which a message image is projected, based on movement information of a mobile. The semiconductor device has a delay period calculation part which calculates a delay period being a period from a first time for projecting the message image onto the first area to a second time when the message image is projectable. Also, the semiconductor device has a second area decision part which adjusts the first area, based on the delay period to decide a second area. Further, the semiconductor device has an image signal conversion part which converts a message image signal according to the second area.
    Type: Grant
    Filed: June 7, 2019
    Date of Patent: September 8, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Koji Yasuda, Hirofumi Kawaguchi, Akihide Takahashi
  • Publication number: 20200202488
    Abstract: A semiconductor device includes an image data acquisition circuit which acquires a plurality of first captured image data and a plurality of second captured image data at a first time and a second time, an adjustment region determination circuit which detects a target object from the plurality of first captured image data, and determines an adjustment region by estimating a position of the target object at the second time, a color adjustment circuit configured to determine a color adjustment gain based on the adjustment region, and perform color balance adjustment processing on the plurality of second captured image data based on the color adjustment gain, and an image synthesis circuit configured to synthesize the plurality of second captured image data so that overlapping regions included in a plurality of images of the plurality of second captured image data overlap each other.
    Type: Application
    Filed: November 4, 2019
    Publication date: June 25, 2020
    Inventors: Hirofumi KAWAGUCHI, Akihide TAKAHASHI
  • Publication number: 20200202581
    Abstract: A semiconductor device includes an image acquisition circuit which acquires a plurality of captured image data obtained by capturing a plurality of images, an estimation source image generation circuit which cancels effects of initial color adjustment processing on each captured image data to generate image data of a plurality of estimation source images, a readjustment circuit which divides each estimation source image into a plurality of processing regions to perform color balance readjustment processing for each processing region, and an image synthesis circuit which synthesizes the image data of the plurality of estimation source images so that overlapping regions included in the estimation source images overlap each other to generate image data of a synthesized image.
    Type: Application
    Filed: November 1, 2019
    Publication date: June 25, 2020
    Inventors: Hirofumi KAWAGUCHI, Akihide TAKAHASHI
  • Publication number: 20200071443
    Abstract: A graft copolymer (C) having a main chain portion of a precursor polymer (A) and a graft portion from a polymer (B), wherein a core portion of the solid product comprises the main chain portion derived from (A), a shell portion comprises the graft portion derived from (B), and the solid product satisfies: Infrared absorption spectroscopic measurement of a section passing through a center (x) of the solid product, a point (z) on a surface where a distance between the center (x) and the surface is shortest, and a middle point (y) of a line connecting the center (x) and the point (z), absorbance (Abs) satisfies X<0.01, Y<0.01, and Z?0.01, wherein X, Y, and Z represent values of Abs (key band of the polymer (B))/Abs (key band of the polymer (A)) at the center (x), the middle point (y) and the point (z).
    Type: Application
    Filed: December 7, 2017
    Publication date: March 5, 2020
    Applicant: MITSUI CHEMICALS, INC.
    Inventors: Akihide MORI, Masahiko OKAMOTO, Katsuyoshi HARADA, Takahiro YAMADA, Shuhei YAMAMOTO, Kiyoshi TAKAHASHI, Kiyoshi YAMAMURA, Koutarou SUZUKI, Ryouichi SEKI, Shinya MATSUNAGA
  • Publication number: 20200018060
    Abstract: A booth includes a replaceable side wall that surrounds an internal space to be used by a user, and the side wall is provided with at least one entrance/exit door.
    Type: Application
    Filed: January 24, 2019
    Publication date: January 16, 2020
    Applicant: FUJI XEROX CO., LTD.
    Inventors: Shu WATANABE, Akihide KAWAMURA, Kunichi YAMASHITA, Akira TAKAHASHI, Yoshihiro SHIBANAI
  • Publication number: 20190389370
    Abstract: A semiconductor device has a position estimation part calculating an estimated position of a mobile at a scheduled time to project a message image, based on movement information of the mobile, a reference image signal output part deciding a reference area being an area to project a reference image, based on a relative positional relation between the mobile at the estimated position and the projection area, and outputting a reference image signal being a signal of the reference image, a test image signal acquisition part acquiring a test image signal being a signal of an image obtained by imaging the reference area with the reference image projected thereon, and an image adjustment part adjusting the message image signal, based on the reference image signal and the test image signal.
    Type: Application
    Filed: June 7, 2019
    Publication date: December 26, 2019
    Inventors: Hirofumi KAWAGUCHI, Koji YASUDA, Akihide TAKAHASHI
  • Publication number: 20190389368
    Abstract: To provide a semiconductor device which suppresses a message image projected by a mobile from varying from a desired position. A semiconductor device has a first area decision part which decides a first area onto which a message image is projected, based on movement information of a mobile. The semiconductor device has a delay period calculation part which calculates a delay period being a period from a first time for projecting the message image onto the first area to a second time when the message image is projectable. Also, the semiconductor device has a second area decision part which adjusts the first area, based on the delay period to decide a second area. Further, the semiconductor device has an image signal conversion part which converts a message image signal according to the second area.
    Type: Application
    Filed: June 7, 2019
    Publication date: December 26, 2019
    Inventors: Koji YASUDA, Hirofumi Kawaguchi, Akihide Takahashi
  • Patent number: 9484296
    Abstract: At least one via level dielectric layer and at least one line level dielectric layer are sequentially formed over an array of device structures. Conductive line structures are formed within the at least one line level dielectric layer. A mask layer is applied over the conductive line structures, and is lithographically patterned to form opening therein. Portions of the conductive line structures are removed from underneath the openings in the patterned mask layer to form via cavities. The via cavities are vertically extended through the at least one via level dielectric layer employing a combination of the mask layer and the at least one line level dielectric layer as an etch mask. At least one conductive material can be deposited in the via cavities to form conductive via structures, which, in conjunction with the conductive line structures, constitute integrated line and via structures.
    Type: Grant
    Filed: February 12, 2015
    Date of Patent: November 1, 2016
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Akihide Takahashi, Ryoichi Honma
  • Publication number: 20160240476
    Abstract: At least one via level dielectric layer and at least one line level dielectric layer are sequentially formed over an array of device structures. Conductive line structures are formed within the at least one line level dielectric layer. A mask layer is applied over the conductive line structures, and is lithographically patterned to form opening therein. Portions of the conductive line structures are removed from underneath the openings in the patterned mask layer to form via cavities. The via cavities are vertically extended through the at least one via level dielectric layer employing a combination of the mask layer and the at least one line level dielectric layer as an etch mask. At least one conductive material can be deposited in the via cavities to form conductive via structures, which, in conjunction with the conductive line structures, constitute integrated line and via structures.
    Type: Application
    Filed: February 12, 2015
    Publication date: August 18, 2016
    Inventors: Akihide TAKAHASHI, Ryoichi HONMA