Patents by Inventor Akihiko Araki
Akihiko Araki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11061851Abstract: A computer system includes a plurality of servers connected to each other via a communication line, each server including a memory and a processor, an OS program and a storage program. The storage program is executed by the processor, and one of the plurality of servers acts as a request source server while one of the other servers acts as a request destination server. When the request source server reads data from the request destination server, the processor of the request source server executes the storage program to transmit a data read request to the request destination server. The processor of the request destination server then executes a storage memory driver incorporated in the OS program to read the requested data from an own memory and transmit the read data to the request source server. The request source server then executes the storage program to acquire the data.Type: GrantFiled: July 28, 2016Date of Patent: July 13, 2021Assignee: HITACHI, LTD.Inventors: Noboru Morishita, Masakuni Agetsuma, Akihiko Araki, Tomoki Sekiyama
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Patent number: 10990468Abstract: A computing system that can maintain reliability required of a storage program while causing the storage program to operate on an operating system (OS) is provided. A processor of the computing system executes an OS controlling a hardware device and a storage program operating on the OS and using the hardware device via the OS. The OS identifies an error status of the hardware device when receiving a notification of an error that has occurred to the hardware device, and notifies the storage program that operates on the OS of the error status when the error status satisfies a predetermined condition. The storage program determines error handling on the hardware device on the basis of the error status, and requests the OS to perform the determined error handling. The OS performs the determined error handling on the hardware device.Type: GrantFiled: March 14, 2016Date of Patent: April 27, 2021Assignee: HITACHI, LTD.Inventors: Akihiko Araki, Masakuni Agetsuma, Sachie Tajima, Takanobu Suzuki, Masanori Takada
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Patent number: 10579275Abstract: This storage system comprises a block interface, a block control unit, a file control unit, and shared memory. The file control unit and block control unit are coupled via a first memory-through path structured to pass through a first area of the shared memory, and via a second memory-through path structured to pass through a second area of the shared memory. The block control unit has a protocol control unit and a virtual driver; exchanges control information for the file control unit with the file control unit via the first memory-through path; uses the virtual driver to convert an I/O request passed from the file control unit via the second memory-through path and processes the result with a protocol processing unit; and bypasses the virtual driver and uses the protocol processing unit to process a block I/O request transferred from the block interface via a physical path.Type: GrantFiled: July 27, 2015Date of Patent: March 3, 2020Assignee: HITACHI, LTD.Inventors: Akihiko Araki, Yusuke Nonaka, Noboru Morishita
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Patent number: 10496444Abstract: By assigning a physically continuous memory area to a virtual storage apparatus operated on an OS, the performance of the virtual storage apparatus is secured. A processor operates an OS, and the processor executes a plurality of processes on the OS. The plurality of processes includes a first virtual storage apparatus. The first virtual storage apparatus executes an I/O process, and includes a cache for storing data that is subjected to the I/O process. The processor assigns a resource in a computer to the plurality of processes, and the processor creates area information that indicates physical addresses assigned to the processes in a memory. On the basis of the area information, the processor selects a continuous area, which is a physically continuous area from the memory and assigns the continuous area to the cache.Type: GrantFiled: October 2, 2015Date of Patent: December 3, 2019Assignee: HITACHI, LTD.Inventors: Sachie Tajima, Masakuni Agetsuma, Takanobu Suzuki, Akihiko Araki
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Patent number: 10353613Abstract: When mounting hardware which is coupled to another portion by a plurality of paths with different applications, despite the hardware being a single device, and a failure occurs in any of the paths, there is a risk that the failure may propagate to other components unless the other paths are also blocked. In order to solve the problem described above, in a storage apparatus to which a device coupled by a plurality of coupling paths with different applications can be mounted, the present invention determines a block range at the time of an occurrence of a failure to be a device and a plurality of coupling paths coupled to the device, manages the block range, and upon an occurrence of a failure, executes failure handling which involves blocking an appropriate block range determined in advance by referring to the information.Type: GrantFiled: November 12, 2014Date of Patent: July 16, 2019Assignee: Hitachi, Ltd.Inventors: Akihiko Araki, Yusuke Nonaka, Masanori Takada, Naoya Okada
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Publication number: 20190095382Abstract: A computer system includes a plurality of servers connected to each other via a communication line, each server including a memory and a processor, an OS program and a storage program. The storage program is executed by the processor, and one of the plurality of servers acts as a request source server while one of the other servers acts as a request destination server. When the request source server reads data from the request destination server, the processor of the request source server executes the storage program to transmit a data read request to the request destination server. The processor of the request destination server then executes a storage memory driver incorporated in the OS program to read the requested data from an own memory and transmit the read data to the request source server. The request source server then executes the storage program to acquire the data.Type: ApplicationFiled: July 28, 2016Publication date: March 28, 2019Inventors: Noboru MORISHITA, Masakuni AGETSUMA, Akihiko ARAKI, Tomoki SEKIYAMA
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Publication number: 20190026179Abstract: A computing system that can maintain reliability required of a storage program while causing the storage program to operate on an operating system (OS) is provided. A processor of the computing system executes an OS controlling a hardware device and a storage program operating on the OS and using the hardware device via the OS. The OS identifies an error status of the hardware device when receiving a notification of an error that has occurred to the hardware device, and notifies the storage program that operates on the OS of the error status when the error status satisfies a predetermined condition. The storage program determines error handling on the hardware device on the basis of the error status, and requests the OS to perform the determined error handling. The OS performs the determined error handling on the hardware device.Type: ApplicationFiled: March 14, 2016Publication date: January 24, 2019Inventors: Akihiko ARAKI, Masakuni AGETSUMA, Sachie TAJIMA, Takanobu SUZUKI, Masanori TAKADA
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Publication number: 20180203733Abstract: By assigning a physically continuous memory area to a virtual storage apparatus operated on an OS, the performance of the virtual storage apparatus is secured. A processor operates an OS, and the processor executes a plurality of processes on the OS. The plurality of processes includes a first virtual storage apparatus. The first virtual storage apparatus executes an I/O process, and includes a cache for storing data that is subjected to the I/O process. The processor assigns a resource in a computer to the plurality of processes, and the processor creates area information that indicates physical addresses assigned to the processes in a memory. On the basis of the area information, the processor selects a continuous area, which is a physically continuous area from the memory and assigns the continuous area to the cache.Type: ApplicationFiled: October 2, 2015Publication date: July 19, 2018Inventors: Sachie TAJIMA, Masakuni AGETSUMA, Takanobu SUZUKI, Akihiko ARAKI
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Publication number: 20180173721Abstract: This storage system comprises a block interface, a block control unit, a file control unit, and shared memory. The file control unit and block control unit are coupled via a first memory-through path structured to pass through a first area of the shared memory, and via a second memory-through path structured to pass through a second area of the shared memory. The block control unit has a protocol control unit and a virtual driver; exchanges control information for the file control unit with the file control unit via the first memory-through path; uses the virtual driver to convert an I/O request passed from the file control unit via the second memory-through path and processes the result with a protocol processing unit; and bypasses the virtual driver and uses the protocol processing unit to process a block I/O request transferred from the block interface via a physical path.Type: ApplicationFiled: July 27, 2015Publication date: June 21, 2018Applicant: Hitachi, Ltd.Inventors: Akihiko ARAKI, Yusuke NONAKA, Noboru MORISHITA
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Publication number: 20170277914Abstract: When mounting hardware which is coupled to another portion by a plurality of paths with different applications, despite the hardware being a single device, and a failure occurs in any of the paths, there is a risk that the failure may propagate to other components unless the other paths are also blocked. In order to solve the problem described above, in a storage apparatus to which a device coupled by a plurality of coupling paths with different applications can be mounted, the present invention determines a block range at the time of an occurrence of a failure to be a device and a plurality of coupling paths coupled to the device, manages the block range, and upon an occurrence of a failure, executes failure handling which involves blocking an appropriate block range determined in advance by referring to the information.Type: ApplicationFiled: November 12, 2014Publication date: September 28, 2017Inventors: Akihiko ARAKI, Yusuke NONAKA, Masanori TAKADA, Naoya OKADA
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Patent number: 9696922Abstract: A storage controller has a processor, a volatile first cache memory that is coupled to the processor and that temporarily stores data, a nonvolatile second cache memory that is coupled to a microprocessor and that temporarily stores data, and a battery that is configured to supply electrical power to at least the processor and the first cache memory when a power stoppage has occurred. The second cache memory includes a dirty data area for storing dirty data, which is data that is not stored in the storage device, and a remaining area other than the dirty data area. When a power stoppage has occurred, the processor stores as target data in the remaining area of the second cache memory either all or a part of the data stored in the first cache memory.Type: GrantFiled: December 24, 2013Date of Patent: July 4, 2017Assignee: Hitachi, Ltd.Inventors: Naoya Okada, Yusuke Nonaka, Akihiko Araki, Shintaro Kudo, Makio Mizuno
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Patent number: 9569130Abstract: A storage system 100, which has a plurality of flash packages 230, has a function for minimizing the imbalance of the number of deletions of each block inside the flash package 230 and a block-unit capacity virtualization function, and efficiently manifests lessening of the imbalance of the number of deletions and reduction in the data storage capacity for the entire storage system 100 by having functions for calculating the number of deletions and the data occupancy of each flash package 230, and for transferring data between the flash packages 230 on the basis of the values of these number of deletions and data occupancy.Type: GrantFiled: December 16, 2015Date of Patent: February 14, 2017Assignee: Hitachi, Ltd.Inventors: Akira Yamamoto, Sadahiro Sugimoto, Akihiko Araki, Masayuki Yamamoto
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Patent number: 9471434Abstract: When a failure occurs in a storage system controller, the controller reboots after completing prescribed failure processing for respective control parts. Upon detecting a failure, first, second, and third control parts of the controller perform respective failure processing. The first control part controls block access requests, the second control part controls file system access, and the third control part manages the second control part. The first control part and third control part write prescribed information to a storage area and reboot at least a portion of the controller upon detecting the failure.Type: GrantFiled: July 22, 2013Date of Patent: October 18, 2016Assignee: HITACHI, LTD.Inventors: Akihiko Araki, Yusuke Nonaka, Masanori Takada
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Publication number: 20160196184Abstract: When a failure occurs, the present invention makes it possible to reboot after completing prescribed failure processing for respective control parts. A storage system 10 comprises a controller 100 and a logical volume 23. The controller 100 comprises a processor 140 and a memory 150 that is used by the processor, and uses the processor to realize a plurality of control parts 101, 102, and 103. A block OS 101, which is an example of a first control part, controls a block access request to a disk device 21 (logical volume 23). A file OS 103, which is an example of a second control part, is managed by a hypervisor 102. When a failure has occurred inside the controller, the controller reboots after confirming that prescribed failure processing has been completed for each OS 101, 102, and 103.Type: ApplicationFiled: July 22, 2013Publication date: July 7, 2016Applicant: HITACHI, LTD.Inventors: Akihiko ARAKI, Yusuke NONAKA, Masanori TAKADA
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Publication number: 20160103629Abstract: A storage system 100, which has a plurality of flash packages 230, has a function for minimizing the imbalance of the number of deletions of each block inside the flash package 230 and a block-unit capacity virtualization function, and efficiently manifests lessening of the imbalance of the number of deletions and reduction in the data storage capacity for the entire storage system 100 by having functions for calculating the number of deletions and the data occupancy of each flash package 230, and for transferring data between the flash packages 230 on the basis of the values of these number of deletions and data occupancy.Type: ApplicationFiled: December 16, 2015Publication date: April 14, 2016Inventors: Akira YAMAMOTO, Sadahiro SUGIMOTO, Akihiko ARAKI, Masayuki YAMAMOTO
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Patent number: 9244622Abstract: A storage system 100, which has a plurality of flash packages 230, has a function for minimizing the imbalance of the number of deletions of each block inside the flash package 230 and a block-unit capacity virtualization function, and efficiently manifests lessening of the imbalance of the number of deletions and reduction in the data storage capacity for the entire storage system 100 by having functions for calculating the number of deletions and the data occupancy of each flash package 230, and for transferring data between the flash packages 230 on the basis of the values of these number of deletions and data occupancy.Type: GrantFiled: December 12, 2014Date of Patent: January 26, 2016Assignee: Hitachi, Ltd.Inventors: Akira Yamamoto, Sadahiro Sugimoto, Akihiko Araki, Masayuki Yamamoto
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Patent number: 9183217Abstract: The present invention aims at improving the performance of a compression function in a storage system, and solves the prior art problem of having to decompress a whole compression unit even if a read request or a write request targets only a portion smaller than the compression unit, causing increase of overhead of decompression processing and elongation of processing time, and deteriorating performance. The present invention prevents unnecessary decompression processing and reduces the overhead of processing by suppressing the range of decompression processing to a minimum portion according to the relationship between the read/write request range and the compression unit.Type: GrantFiled: October 18, 2012Date of Patent: November 10, 2015Assignee: HITACHI, LTD.Inventors: Akihiko Araki, Akira Yamamoto, Kenta Shiga
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Publication number: 20150317093Abstract: A storage controller has a processor, a volatile first cache memory that is coupled to the processor and that temporarily stores data, a nonvolatile second cache memory that is coupled to a microprocessor and that temporarily stores data, and a battery that is configured to supply electrical power to at least the processor and the first cache memory when a power stoppage has occurred. The second cache memory includes a dirty data area for storing dirty data, which is data that is not stored in the storage device, and a remaining area other than the dirty data area. When a power stoppage has occurred, the processor stores as target data in the remaining area of the second cache memory either all or a part of the data stored in the first cache memory.Type: ApplicationFiled: December 24, 2013Publication date: November 5, 2015Applicant: Hitachi, Ltd.Inventors: Naoya OKADA, Yusuke NONAKA, Akihiko ARAKI, Shintaro KUDO, Makio MIZUNO
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Patent number: 9081690Abstract: An embodiment of this invention divides a cache memory of a storage system into a plurality of partitions and information in one or more of the partitions is composed of data different from user data and including control information. The storage system dynamically swaps data between an LU storing control information and a cache partition. Through this configuration, in a storage system having an upper limit in the capacity of the cache memory, a large amount of control information can be used while access performance to control information is kept.Type: GrantFiled: October 6, 2014Date of Patent: July 14, 2015Assignee: Hitachi, Ltd.Inventors: Akihiko Araki, Yusuke Nonaka
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Patent number: 9026754Abstract: Storage apparatus and data management methods provide for high-speed copying of a compressed data volume. A control unit of the storage apparatus divides a pool into a plurality of chunks including a plurality of pages storing data, compresses data which is written to a logical volume by a host, and assigns one of the plurality of chunks to a compressed data logical volume which stores the compressed data. When the compressed data logical volume is copied, the control unit makes a page length of the chunk assigned to the compressed data logical volume that is a copy source equivalent to a page length of the chunk assigned to the compressed data logical volume that is the copy destination.Type: GrantFiled: May 11, 2012Date of Patent: May 5, 2015Assignee: Hitachi, Ltd.Inventors: Takaki Matsushita, Akira Deguchi, Hiroaki Akutsu, Akihiko Araki