Abstract: A path test signal generator and checker which can achieve a path test by effectively generating a path test signal in a system handling synchronous transport modules STM-Ns with an order higher than that of the basic interface. A test pattern generator generates a continuous PN pattern intermittently, inserts a predetermined logical value in locations of the section overhead and path overhead in a transmission frame while suspending the generation of the path test signal in those locations, and inserts the continuous PN pattern in the entire columns of the payload of the transmission frame. A path overhead insertion circuit rewrites the predetermined logical value inserted in the location of the path overhead into the path overhead. The multiplex section terminating circuit rewrites the predetermined logical value inserted in the location of the MSOH (multiplex section overhead) to the MSOH, and the logical value inserted in the location of the RSOH (regenerator section overhead) to the RSOH.

Abstract: A bit synchronization circuit receives a first clock signal, a higher-frequency second clock signal, and digital data synchronized with the first clock signal. From the first clock signal, the circuit generates a write control signal that cyclically selects memory elements from a group of memory elements, and stores the digital data in the selected memory elements. From the second clock signal, the circuit generates a read control signal that cyclically selects memory elements from the same group, and outputs the digital data from the selected memory elements. The circuit also compares the phase of the read and write control signals, and adjusts the phase of the read control signal in response to the phase relation between the write control signal and read control signal.