Abstract: A method of manufacturing a semiconductor device includes forming a first insulating film above a semiconductor substrate, patterning the first insulating film to form a first and a second opening, forming a first sidewall film on side walls of the first and the second openings, etching the semiconductor substrate with the first insulating film and the first sidewall film as a mask to dig down the first opening and the second opening, removing the first sidewall film to form a first offset portion in the first opening and a second offset portion in the second opening, the first and the second offset portion including a part of a surface of the semiconductor substrate, and etching a bottom of the first opening with the first insulating film as a mask.

Abstract: To accurately measure power source noise generated inside an integrated circuit, the power source noise measuring device comprises: a mutual inductor pair placed inside an integrated circuit, the mutual inductor pair including (i) a first inductor connected to between power source voltages of the integrated circuit and (ii) a second inductor arranged opposite the first inductor, the both ends of which second inductor are connected to external output terminals; and a power source noise measuring unit which measures power source noise of the integrated circuit on the basis of a voltage waveform output from the second inductor of said mutual inductor pair via the external output terminals.

Abstract: To accurately measure power source noise generated inside an integrated circuit, the power source noise measuring device comprises: a mutual inductor pair placed inside an integrated circuit, the mutual inductor pair including (i) a first inductor connected to between power source voltages of the integrated circuit and (ii) a second inductor arranged opposite the first inductor, the both ends of which second inductor are connected to external output terminals; and a power source noise measuring unit which measures power source noise of the integrated circuit on the basis of a voltage waveform output from the second inductor of said mutual inductor pair via the external output terminals.

Abstract: To accurately measure power source noise generated inside an integrated circuit, the power source noise measuring device comprises: a mutual inductor pair placed inside an integrated circuit, the mutual inductor pair including (i) a first inductor connected to between power source voltages of the integrated circuit and (ii) a second inductor arranged opposite the first inductor, the both ends of which second inductor are connected to external output terminals; and a power source noise measuring unit which measures power source noise of the integrated circuit on the basis of a voltage waveform output from the second inductor of said mutual inductor pair via the external output terminals.

Abstract: The present invention provides a semiconductor device having a plurality of functional blocks and a select signal generation circuit for supplying a select signal to a functional block to be operated out of the plurality of blocks. A clock generation unit in the function clock, to which the select signal and a system clock are supplied, generates a control clock based on the system clock when the select signal is being supplied, and stops generation of the control clock when the select signal is not being supplied. When the select signal is not received, a dynamic circuit provided inside the functional block does not operate since the control clock is not supplied. When the select signal is received, the control clock is supplied and the dynamic circuit repeats precharge and discharge for each clock cycle, and performs operation to execute a predetermined function, and consumes power.

Abstract: To provide a semiconductor memory device capable of increasing its drive capability at operating time while reducing a leak current at standby time without the s need to make a significant change to the design of an existing semiconductor memory device a semiconductor memory device having a memory cell comprises: a latch section that includes a transistor having a back gate to which a back gate voltage is supplied; a memory cell that includes a transfer gate constituting the memory cell the transfer gate being subjected to switching control by a word line signal and having a lo back gate to which a back gate voltage is supplied; and a back gate voltage control circuit that controls the back gate voltage based on an address signal.

Abstract: To accurately measure power source noise generated inside an integrated circuit, the power source noise measuring device comprises: a mutual inductor pair placed inside an integrated circuit, the mutual inductor pair including (i) a first inductor connected to between power source voltages of the integrated circuit and (ii) a second inductor arranged opposite the first inductor, the both ends of which second inductor are connected to external output terminals; and a power source noise measuring unit which measures power source noise of the integrated circuit on the basis of a voltage waveform output from the second inductor of said mutual inductor pair via the external output terminals.

Abstract: The present invention provides a semiconductor device having a plurality of functional blocks and a select signal generation circuit for supplying a select signal to a functional block to be operated out of the plurality of blocks. A clock generation unit in the function clock, to which the select signal and a system clock are supplied, generates a control clock based on the system clock when the select signal is being supplied, and stops generation of the control clock when the select signal is not being supplied. When the select signal is not received, a dynamic circuit provided inside the functional block does not operate since the control clock is not supplied. When the select signal is received, the control clock is supplied and the dynamic circuit repeats precharge and discharge for each clock cycle, and performs operation to execute a predetermined function, and consumes power.

Abstract: An insulated gate type semiconductor device comprised of a semiconductor layer serving as an active region isolated from a semiconductor substrate by a substrate isolation insulating film and a T-shaped gate electrode comprised of a trunk-shaped main gate electrode and a crosspiece-shaped conductor pattern provided on the semiconductor layer, wherein the thickness of the gate insulating film directly under the crosspiece-shaped conductor pattern is made greater than the thickness of the gate insulating film directly under the main gate electrode, whereby it is possible to prevent short-circuits between electrodes, prevent short-circuits between separators, and prevent an increase of the parasitic capacitance.

Abstract: In a packaged integrated circuit, the package inductance limits the rate at which off-chip current may be varied in response to a change in on-chip current demand of the integrated circuit. The present invention provides an on-chip voltage regulator circuit for regulating multi-cycle voltage fluctuations of an integrated circuit associated with changes in current demand of the integrated circuit. The voltage regulator sources current to prevent an undervoltage conditions and sinks current to prevent an overvoltage condition.

Abstract: In a packaged integrated circuit, the package inductance limits the rate at which off-chip current may be varied in response to a change in on-chip current demand of the integrated circuit. The present invention provides an on-chip voltage regulator circuit for regulating multi-cycle voltage fluctuations of an integrated circuit associated with changes in current demand of the integrated circuit. The voltage regulator sources current to prevent an undervoltage conditions and sinks current to prevent an overvoltage condition.

Abstract: In a packaged integrated circuit, the package inductance limits the rate at which off-chip current may be varied in response to a change in on-chip current demand of the integrated circuit. The present invention provides an on-chip voltage regulator circuit for regulating multi-cycle voltage fluctuations of an integrated circuit associated with changes in current demand of the integrated circuit. The voltage regulator sources current to prevent an undervoltage conditions and sinks current to prevent an overvoltage condition.

Abstract: A transistor which has a stable characteristic and which can prevent tilted ions from penetrating through a grain boundary to a channel region when ions are implanted at an angle so as to form impurity layers while a gate electrode is used as a mask. A gate electrode comprises a two-layer structure of a lower film and an upper film formed on a gate insulation film on the surface of a semiconductor substrate. The thickness of the lower film is made greater than the range of ions in the thickness wise direction in the film when the ions are implanted to the sidewalls of the lower film.

Abstract: A complement reset multiplexer latch is provided. The complement reset multiplexer latch selectively regenerates a first or a second data input signal on an output node. To react to rising edges of the first or the second data signal, the complement reset multiplexer latch includes a first and a second rising edge pulse reset control. To react to falling edges of the first or the second data signal, the complement reset multiplexer latch includes a first and a second falling edge pulse reset control. The complement reset multiplexer latch also selectively holds the output node at a stored value responsive to a clock signal. A multiplexer is used to select from the first or the second data input the value that is stored.

Abstract: A complement reset multiplexer latch is provided. The complement reset multiplexer latch selectively regenerates a first or a second data input signal on an output node. To react to rising edges of the first or the second data signal, the complement reset multiplexer latch includes a first and a second rising edge pulse reset control. To react to falling edges of the first or the second data signal, the complement reset multiplexer latch includes a first and a second falling edge pulse reset control. The complement reset multiplexer latch also selectively holds the output node at a stored value responsive to a clock signal. A multiplexer is used to select from the first or the second data input the value that is stored.

Abstract: A semiconductor device, having a multi-layer interconnection structure, is provided which comprises a semiconductor substrate and a plurality of interlayer insulating films formed on the semiconductor substrate. A plurality of conductive leads are formed in the interlayer insulating films. In one of the interlayer insulating films having conductive lead or leads, at least one conductive plug is formed vertically to connect the conductive leads in different interlayer insulating films. Further, adjacent conductive leads may be formed in an adjacent interlayer insulating films are connected together to form a unified conductive lead.

Abstract: A semiconductor device, having a multi-layer interconnection structure, is provided which comprises a semiconductor substrate and a plurality of interlayer insulating films formed on the semiconductor substrate. A plurality of conductive leads are formed in the interlayer insulating films. In one of the interlayer insulting films having conductive lead or leads, at least one conductive plug is formed vertically to connect the conductive leads in different interlayer insulating films. Further, adjacent conductive leads may be formed in an adjacent interlayer insulating films are connected together to form a unified conductive lead.

Abstract: There is described a method of manufacturing a semiconductor device for the purpose of preventing damage to a lower wiring layer, wherein wiring elements of dual damascene structure are formed on the lower wiring layer. Under the method, a first silicon nitride film, a first silicon oxide film, a second silicon nitride film, and a second silicon oxide film are formed, in this sequence, on a lower wiring layer. A via hole is formed at a position above the lower wiring layer so as to pass through the second silicon oxide film and the second silicon nitride film. A photoresist is embedded into the via hole so as to cover the internal wall surface thereof. After formation of a protective film from the photoresist, predetermined portions of the second silicon oxide film and the second silicon nitride film are removed, thus forming a wiring trench.

Abstract: A transistor which has a stable characteristic and which can prevent tilted ions from penetrating through a grain boundary to a channel region when ions are implanted at an angle so as to form impurity layers while a gate electrode is used as a mask. A gate electrode comprises a two-layer structure of a lower film and an upper film formed on a gate insulation film on the surface of a semiconductor substrate. The thickness of the lower film is made greater than the range of ions in the thicknesswise direction in the film when the ions are implanted to the sidewalls of the lower film.

Abstract: A semiconductor device is formed with interconnections having reduced electric resistance. The semiconductor device comprises an upper wiring formed on an insulating film with a barrier metal therebetween, a conductive plug formed in a plugging space of the insulating film and electrically connected to the upper wiring at an opening of the plugging space, and a sidewall formed on a side surface of the upper wiring, the bottom of the sidewall covering the opening of the plugging space not covered by the upper wiring.