Abstract: A semiconductor module includes a stacked substrate includes an insulating plate and first and second circuit boards arranged on the insulating plate, a semiconductor element arranged on the first circuit board, and a metal wiring board having a first bonding portion bonded to an upper surface of the semiconductor element via a first bonding material. The first bonding portion includes a first plate-shaped portion that has at a lower surface thereof, a boss protruding toward the semiconductor element, and at an upper surface thereof, a first recess at a position corresponding to a position immediately above the boss and multiple second recesses. At the upper surface of the first plate-shaped portion, each of the second recesses has an opening area smaller than an opening area of the first recess.

Abstract: Provided is a semiconductor module including: an insulating circuit board having a circuit pattern formed in one surface; a semiconductor chip placed in the insulating circuit board; and a wiring portion for electrically connecting the semiconductor chip and the circuit pattern. The wiring portion includes a chip connecting portion connected to the semiconductor chip. A surface of the chip connecting portion includes: a plurality of concave portions; and a flat portion disposed between two concave portions.

Abstract: An object of the present invention is to improve the reliability of a semiconductor device. A semiconductor device has a first lead group comprised of a plurality of first leads, a second lead group comprised of a plurality of second leads, and a first suspension lead arranged between the first lead group and the second lead group. Further, the semiconductor device has a first tape attached to each of the first leads, the first suspension lead, and some of the second leads, and a second tape attached to each of the second leads. Further, the first tape has a lead holding part attached to each of the first leads, and a tape supporting part attached to the first suspension lead and some of the second leads and is attached to a position farther from wire connecting portion than the lead holding part.

Abstract: An object of the present invention is to improve the reliability of a semiconductor device. A semiconductor device has a first lead group comprised of a plurality of first leads, a second lead group comprised of a plurality of second leads, and a first suspension lead arranged between the first lead group and the second lead group. Further, the semiconductor device has a first tape attached to each of the first leads, the first suspension lead, and some of the second leads, and a second tape attached to each of the second leads. Further, the first tape has a lead holding part attached to each of the first leads, and a tape supporting part attached to the first suspension lead and some of the second leads and is attached to a position farther from wire connecting portion than the lead holding part.

Abstract: An object of the present invention is to improve the reliability of a semiconductor device. A semiconductor device has a first lead group comprised of a plurality of first leads, a second lead group comprised of a plurality of second leads, and a first suspension lead arranged between the first lead group and the second lead group. Further, the semiconductor device has a first tape attached to each of the first leads, the first suspension lead, and some of the second leads, and a second tape attached to each of the second leads. Further, the first tape has a lead holding part attached to each of the first leads, and a tape supporting part attached to the first suspension lead and some of the second leads and is attached to a position farther from wire connecting portion than the lead holding part.

Abstract: An object of the present invention is to improve the reliability of a semiconductor device. A semiconductor device has a first lead group comprised of a plurality of first leads, a second lead group comprised of a plurality of second leads, and a first suspension lead arranged between the first lead group and the second lead group. Further, the semiconductor device has a first tape attached to each of the first leads, the first suspension lead, and some of the second leads, and a second tape attached to each of the second leads. Further, the first tape has a lead holding part attached to each of the first leads, and a tape supporting part attached to the first suspension lead and some of the second leads and is attached to a position farther from wire connecting portion than the lead holding part.

Abstract: A semiconductor device capable of improving the flexibility of designing electrical lead patterns for connection from chips via a substrate to external terminals by appropriately arranging the substrate structure and layout of more than one address signal as commonly shared by four separate chips is disclosed. In a surface mount type package of ball grid array (BGA), four chips 1 are mounted on a substrate 2 in such a manner such these are laid out in the form of an array of two rows and two columns. These four chips 1 are such that regarding the upper side and lower side, these are in linear symmetry with respect to a center line extending in a direction along long side edges of the substrate 2.

Abstract: The present invention provides a thin, inexpensive, high-performance semiconductor device provided with busbar leads, power leads and signal leads. A portion of the power lead connected to the busbar lead is depressed toward a major surface of a semiconductor chip to form depressed portion, and the depressed portion is bonded to the major surface of the semiconductor chip by an adhesive layer. The signal lead and the busbar lead are spaced apart from the major surface of the semiconductor chip.

Abstract: A LOC type semiconductor device comprises a semiconductor chip having a main surface in which semiconductor elements and a plurality of bonding pads are formed, and a back surface opposite the main surface; a plurality of leads each having an inner part and an outer part, and including a plurality of first leads having inner end portions extended on the main surface of the semiconductor chip and a plurality of second leads having inner end portions terminating near the semiconductor chip; bonding wires electrically connecting the bonding pads to bonding portions of the inner parts of the first and the second leads; and a sealing member sealing the semiconductor chip therein. A first bending portion is formed in the inner part of each second lead to prevent the sealing member from transformation by forming the sealing member in satisfactory resin balance between an upper portion and a lower portion of the sealing member.

Abstract: A LOC type semiconductor device comprises a semiconductor chip having a main surface in which semiconductor elements and a plurality of bonding pads are formed, and a back surface opposite the main surface; a plurality of leads each having an inner part and an outer part, and including a plurality of first leads having inner end portions extended on the main surface of the semiconductor chip and a plurality of second leads having inner end portions terminating near the semiconductor chip; bonding wires electrically connecting the bonding pads to bonding portions of the inner parts of the first and the second leads; and a sealing member sealing the semiconductor chip therein. A first bending portion is formed in the inner part of each second lead to prevent the sealing member from transformation by forming the sealing member in satisfactory resin balance between an upper portion and a lower portion of the sealing member.

Abstract: A semiconductor device capable of improving the flexibility of designing electrical lead patterns for connection from chips via a substrate to external terminals by appropriately arranging the substrate structure and layout of more than one address signal as commonly shared by four separate chips is disclosed. In a surface mount type package of ball grid array (BGA), four chips 1 are mounted on a substrate 2 in such a manner such these are laid out in the form of an array of two rows and two columns. These four chips 1 are such that regarding the upper side and lower side, these are in linear symmetry with respect to a center line extending in a direction along long side edges of the substrate 2.

Abstract: A LOC type semiconductor device comprises a semiconductor chip having a main surface in which semiconductor elements and a plurality of bonding pads are formed, and a back surface opposite the main surface; a plurality of leads each having an inner part and an outer part, and including a plurality of first leads having inner end portions extended on the main surface of the semiconductor chip and a plurality of second leads having inner end portions terminating near the semiconductor chip; bonding wires electrically connecting the bonding pads to bonding portions of the inner parts of the first and the second leads; and a sealing member sealing the semiconductor chip therein. A first bending portion is formed in the inner part of each second lead to prevent the sealing member from transformation by forming the sealing member in satisfactory resin balance between an upper portion and a lower portion of the sealing member.

Abstract: A LOC type semiconductor device comprises a semiconductor chip having a main surface in which semiconductor elements and a plurality of bonding pads are formed, and a back surface opposite the main surface; a plurality of leads each having an inner part and an outer part, and including a plurality of first leads having inner end portions extended on the main surface of the semiconductor chip and a plurality of second leads having inner end portions terminating near the semiconductor chip; bonding wires electrically connecting the bonding pads to bonding portions of the inner parts of the first and the second leads; and a sealing member sealing the semiconductor chip therein. A first bending portion is formed in the inner part of each second lead to prevent the sealing member from transformation by forming the sealing member in satisfactory resin balance between an upper portion and a lower portion of the sealing member.

Abstract: A semiconductor device capable of improving the flexibility of designing electrical lead patterns for connection from chips via a substrate to external terminals by appropriately arranging the substrate structure and layout of more than one address signal as commonly shared by four separate chips is disclosed. In a surface mount type package of ball grid array (BGA), four chips 1 are mounted on a substrate 2 in such a manner such these are laid out in the form of an array of two rows and two columns. These four chips 1 are such that regarding the upper side and lower side, these are in linear symmetry with respect to a center line extending in a direction along long side edges of the substrate 2.

Abstract: A semiconductor device capable of improving the flexibility of designing electrical lead patterns for connection from chips via a substrate to external terminals by appropriately arranging the substrate structure and layout of more than one address signal as commonly shared by four separate chips is disclosed. In a surface mount type package of ball grid array (BGA), four chips 1 are mounted on a substrate 2 in such a manner such these are laid out in the form of an array of two rows and two columns. These four chips 1 are such that regarding the upper side and lower side, these are in linear symmetry with respect to a center line extending in a direction along long side edges of the substrate 2.

Abstract: A semiconductor device capable of improving the flexibility of designing electrical lead patterns for connection from chips via a substrate to external terminals by appropriately arranging the substrate structure and layout of more than one address signal as commonly shared by four separate chips is disclosed. In a surface mount type package of ball grid array (BGA), four chips 1 are mounted on a substrate 2 in such a manner such these are laid out in the form of an array of two rows and two columns. These four chips 1 are such that regarding the upper side and lower side, these are in linear symmetry with respect to a center line extending in a direction along long side edges of the substrate 2.

Abstract: A semiconductor device capable of improving the flexibility of designing electrical lead patterns for connection from chips via a substrate to external terminals by appropriately arranging the substrate structure and layout of more than one address signal as commonly shared by four separate chips is disclosed. In a surface mount type package of ball grid array (BGA), four chips 1 are mounted on a substrate 2 in such a manner such these are laid out in the form of an array of two rows and two columns. These four chips 1 are such that regarding the upper side and lower side, these are in linear symmetry with respect to a center line extending in a direction along long side edges of the substrate 2.

Abstract: A method is provided for forming a thin, inexpensive, high-performance semiconductor device provided with busbar leads, power leads and signal leads. A portion of the power lead connected to the busbar lead is depressed toward a major surface of a semiconductor chip to form a depressed portion, and the depressed portion is bonded to the major surface of the semiconductor chip by an adhesive layer. The signal lead and the busbar lead are spaced apart from the major surface of the semiconductor chip.

Abstract: A LOC type semiconductor device comprises a semiconductor chip having a main surface in which semiconductor elements and a plurality of bonding pads are formed, and a back surface opposite the main surface; a plurality of leads each having an inner part and an outer part, and including a plurality of first leads having inner end portions extended on the main surface of the semiconductor chip and a plurality of second leads having inner end portions terminating near the semiconductor chip; bonding wires electrically connecting the bonding pads to bonding portions of the inner parts of the first and the second leads; and a sealing member sealing the semiconductor chip therein. A first bending portion is formed in the inner part of each second lead to prevent the sealing member from transformation by forming the sealing member in satisfactory resin balance between an upper portion and a lower portion of the sealing member.

Abstract: The present invention provides a thin, inexpensive, high-performance semiconductor device provided with busbar leads, power leads and signal leads. A portion of the power lead connected to the busbar lead is depressed toward a major surface of a semiconductor chip to form depressed portion, and the depressed portion is bonded to the major surface of the semiconductor chip by an adhesive layer. The signal lead and the busbar lead are spaced apart from the major surface of the semiconductor chip.