Abstract: A semiconductor memory device includes a mask information storage circuit that stores therein mask information indicating an area for which the self refresh operation is not performed among a plurality of areas in a memory cell array, a mask determining circuit that is activated by a self refresh command and generates a match signal in response to a detection of a match between a refresh address and the mask information, and a refresh operation control circuit that disables the self refresh operation in response to an activation of the match signal. When a test mode signal is activated, the mask determining circuit is also activated by the auto refresh command. With this configuration, it is possible to perform a test of a partial array self refresh function without actually entering a self refresh mode.

Abstract: There are provided a semiconductor memory device and others having a preferable operation efficiency and eliminating complicated control when refreshing a memory array divided into a plurality of banks. The semiconductor memory device includes a memory array (10) divided into a plurality of banks (0 to 3) each of which can be controlled independently and its peripheral circuit. Each of the banks 0 to 3 has a refresh counter (24) for generating a row address to be refreshed. A control circuit (20) executes refresh operation for the bank selected according to the bank selection data in accordance with a refresh request having bank selection data for selecting a plurality of banks 0 to 3 in an arbitrary combination. On the other hand, the control circuit (3) performs control no to execute refresh operation for the bank not selected according to the bank selection data.

Abstract: A semiconductor memory device includes a mask information storage circuit that stores therein mask information indicating an area for which the self refresh operation is not performed among a plurality of areas in a memory cell array, a mask determining circuit that is activated by a self refresh command and generates a match signal in response to a detection of a match between a refresh address and the mask information, and a refresh operation control circuit that disables the self refresh operation in response to an activation of the match signal. When a test mode signal is activated, the mask determining circuit is also activated by the auto refresh command. With this configuration, it is possible to perform a test of a partial array self refresh function without actually entering a self refresh mode.

Abstract: There are provided a semiconductor memory device and others having a preferable operation efficiency and eliminating complicated control when refreshing a memory array divided into a plurality of banks. The semiconductor memory device includes a memory array (10) divided into a plurality of banks (0 to 3) each of which can be controlled independently and its peripheral circuit. Each of the banks 0 to 3 has a refresh counter (24) for generating a row address to be refreshed. A control circuit (20) executes refresh operation for the bank selected according to the bank selection data in accordance with a refresh request having bank selection data for selecting a plurality of banks 0 to 3 in an arbitrary combination. On the other hand, the control circuit (3) performs control no to execute refresh operation for the bank not selected according to the bank selection data.

Abstract: A semiconductor memory device of the invention has memory cells arranged at intersections of bit lines and word lines, and comprises a sense amplifier for amplifying a minute potential difference appearing on a bit line pair; a power supply line pair including first and second power supply lines for supplying first and second potentials to the sense amplifier; a pre-charge power supply line for supplying a predetermined pre-charge potential; a power supply line equalize circuit for setting the first and second potentials at the same potential based on the pre-charge potential; a current limit circuit inserted in series in a predetermined current path from the pre-charge power supply line to the power supply line pair; and switch means capable of switching whether or not current flowing from the pre-charge power supply line to the power supply line pair is limited by the current limit circuit based on a control signal.

Abstract: A semiconductor memory device of the invention has memory cells arranged at intersections of bit lines and word lines, and comprises a sense amplifier for amplifying a minute potential difference appearing on a bit line pair; a power supply line pair including first and second power supply lines for supplying first and second potentials to the sense amplifier; a pre-charge power supply line for supplying a predetermined pre-charge potential; a power supply line equalize circuit for setting the first and second potentials at the same potential based on the pre-charge potential; a current limit circuit inserted in series in a predetermined current path from the pre-charge power supply line to the power supply line pair; and switch means capable of switching whether or not current flowing from the pre-charge power supply line to the power supply line pair is limited by the current limit circuit based on a control signal.

Abstract: An output circuit of a semiconductor memory device is provided, which prevents a current from flowing through a pair of output transistors due to their ON-ON state.

Abstract: A test mode setting circuit includes a high voltage detection circuit, an uppermost row address buffer and a row address buffer control circuit for the uppermost row address buffer. When a high voltage is supplied to a common input terminal for the test mode setting, the uppermost row address buffer receives through the common input terminal an uppermost address signal, and provides the uppermost address signal as an uppermost internal row address signal.

Abstract: A semiconductor memory device has address buffer circuits operative to produce address predecoded signals for enabling an addressing system to selectively make memory cell sub-arrays accessible, a prohibit circuit operative to fix address predecoded signal or signals to inactive level for prohibiting the associated memory cell sub-arrays from a service as a data storage and an information storage circuit for storing pieces of test information indicative of the memory cell sub-arrays prohibited from the service, and a manufacturer easily groups the products by the available memory cell sub-arrays after package of the products.

Abstract: In a semiconductor memory device which can perform a parallel test upon a predetermined number of memory cells by using a degenerate address of a plurality of first addresses each corresponding to one memory cell, when a defective memory cell is found by a parallel test using the degenerate address, an address whose space includes the space of the degenerate address is written into only one location of its corresponding redundancy decoder to replace the defective memory cell with its corresponding redundancy memory cell.

Abstract: A dynamic random access memory device periodically refreshes data bits stored in the memory cells for preventing the data bits from destruction, and an autorefreshing unit incorporated in the dynamic random access memory device is responsive to a CAS-Before-RAS signal control for producing an internal row address strobe signal so that the data bits are automatically refreshed with the internal row address strobe signal in a sequence of self-refreshing cycles without any external signal control.

Abstract: A dynamic random access memory device comprises memory cells arranged in rows and columns and storing data bits, respectively, bit line pairs respectively coupled to every two columns of the memory cells for propagating the data bits read out from the memory cells, word lines respectively coupled to the rows of the memory cells and allowing the data bits stored in one of the rows of the memory cells to be read out to the bit line pairs, sense amplifier circuits provided in association with the bit line pairs and selectively coupling the component bit lines to first and second sources of voltage level depending upon the logic level of the data bits, a pair of data signal lines coupled to an output data buffer circuit, a column selector unit coupled between the bit line pairs and the data signal lines and sequentially interconnecting the bit line pairs and the data signal lines in a static column mode of operation, and a precharging unit coupled to the data signal lines and having current paths from the first s

Abstract: For accelerating of a testing operation to determine which memory cell in a memory cell array is replaced with a redundant memory cell, a semiconductor memory device is composed of an address discriminating facility having an activation circuit operative to compare an address indicated by an address signal and the address assigned the memory cell replaced with the redundant memory cell for producing a first controlling signal. A testing operation controlling circuit is responsive to a test mode signal for producing a second controlling signal and a data write-in circuit responsive to the second controlling signal and producing a test bit of logic "1" level and a test bit of logic "0" level. The test bit of logic "1" and the test bit of logic "0" are respectively written into the redundant memory cell and the memory cell array so that an address assigned to the memory cell replaced with the redundant memory cell is discriminated through a read-out operation.

Abstract: A semiconductor memory device having a redundant memory cell group selectable by a redundant decoder operable by a small power consumption is disclosed. The redundant decoder comprises a plurality of address program circuits which store address of a defective memory cell or cells and a control circuit for enabling the address program circuits when at least one defective memory cell is present and disenabling the address program circuits when no defective memory cell is present.