Patents by Inventor Akihiko Kasagi

Akihiko Kasagi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200372321
    Abstract: An information processing method implemented by a computer includes: executing a generation processing that includes generating a first mini-batch by performing data extension processing on learning data and processing to generate a second mini-batch without performing the data extension processing on the learning data; and executing a learning processing by using a neural network, the learning processing being configured to perform first learning by using the first mini-batch, and then perform second learning by using the second mini-batch.
    Type: Application
    Filed: April 29, 2020
    Publication date: November 26, 2020
    Applicant: FUJITSU LIMITED
    Inventors: Akihiro TABUCHI, Akihiko Kasagi
  • Patent number: 10768932
    Abstract: An arithmetic processing circuit includes, a dividing circuit that divides a plurality of data blocks into groups of a number equal to the number of arithmetic processing circuits included in an information processing apparatus, a data selecting circuit that selects respective first data blocks from the plurality of data blocks included in the respective groups, a transmission destination selecting circuit that selects arithmetic processing circuits different from each other as respective transmission destinations from the plurality of arithmetic processing circuits for the respective first data blocks selected by the data selecting circuit based on destination number information obtained by exclusive disjunction operation on identification number information assigned to each arithmetic processing circuit and cyclic number information assigned to each group, and a transmitting circuit that transmits the respective first data blocks selected by the data selecting circuit to the respective arithmetic processing
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: September 8, 2020
    Assignee: FUJITSU LIMITED
    Inventor: Akihiko Kasagi
  • Publication number: 20200192717
    Abstract: An information processing apparatus for controlling a plurality of nodes mutually coupled via a plurality of cables, the apparatus includes: a memory; a processor coupled to the memory, the processor being configured to cause a first node to execute first processing to extract coupling relationship between the plurality of nodes, the first node being one of the plurality of nodes, being sequentially allocated from each of the plurality of nodes, the first processing including executing allocation processing that allocates unique coordinate information to the first node and allocates common coordinate information to nodes excluding the first node; executing transmission processing that causes the first node to transmit first information to each of the cables coupled to the first node; and executing identification processing that identifies a node having received the first information as neighboring node coupled to one of the plurality of cables coupled to the first node.
    Type: Application
    Filed: November 6, 2019
    Publication date: June 18, 2020
    Applicant: FUJITSU LIMITED
    Inventor: Akihiko Kasagi
  • Publication number: 20200167162
    Abstract: A method for controlling an information processing system, the information processing system including multiple information processing devices coupled to each other, each of the multiple information processing devices including multiple main operation devices and multiple aggregate operation devices that are coupled to each other, the method includes: acquiring, by each of the aggregate operation devices, array data items from a main operation device coupled to the concerned aggregate operation device; determining the order of dimensions in which a process is executed and in which the information processing devices are coupled to each other; executing for each of the dimensions in accordance with the order of the dimensions, a process of halving the array data items and distributing the array data items to information processing devices arranged in the dimension; executing a process of transmitting, to information processing devices arranged in the dimension, operation results calculated based on data items.
    Type: Application
    Filed: October 28, 2019
    Publication date: May 28, 2020
    Applicant: FUJITSU LIMITED
    Inventors: Akihiko Kasagi, Takashi Arakawa
  • Patent number: 10558730
    Abstract: A computing method includes: generating first partitioned matrices by partitioning the first matrix by a least common multiple of the M and the N in the row direction and by the N in the column direction; generating second partitioned matrices by partitioning the second matrix by the M in the row direction and by the least common multiple in the column direction; adding a first product of the first partitioned matrices and the second partitioned matrices to a first result matrix; transmitting the first partitioned matrices to computing elements directly connected to that computing element out of other computing elements connected to each other in a torus-like manner in the row direction; transmitting the second partitioned matrices to computing elements directly connected to that computing element out of other computing elements connected to each other in a torus-like manner in the column direction.
    Type: Grant
    Filed: February 13, 2018
    Date of Patent: February 11, 2020
    Assignee: FUJITSU LIMITED
    Inventor: Akihiko Kasagi
  • Patent number: 10387997
    Abstract: An information processing device includes a first memory and a processor. The processor includes a circuit and a second memory. The circuit calculates a first value from a plurality of third pixels that are located above an interpolation pixel from among a plurality of first pixels, calculates a second value from a plurality of fourth pixels that are located above the interpolation pixel from among an plurality of second pixels, calculates a third value from a plurality of fifth pixels that are located below the interpolation pixel, calculates a fourth value from a plurality of sixth pixels that are located below the interpolation pixel, calculates a first gradient value from the first and third values, calculates a second gradient value from the second and fourth values, determines an edge direction according to the first gradient value and the second gradient value, and calculates a pixel value of an interpolation pixel.
    Type: Grant
    Filed: October 23, 2017
    Date of Patent: August 20, 2019
    Assignee: FUJITSU LIMITED
    Inventor: Akihiko Kasagi
  • Publication number: 20190138302
    Abstract: An arithmetic processing circuit includes, a dividing circuit that divides a plurality of data blocks into groups of a number equal to the number of arithmetic processing circuits included in an information processing apparatus, a data selecting circuit that selects respective first data blocks from the plurality of data blocks included in the respective groups, a transmission destination selecting circuit that selects arithmetic processing circuits different from each other as respective transmission destinations from the plurality of arithmetic processing circuits for the respective first data blocks selected by the data selecting circuit based on destination number information obtained by exclusive disjunction operation on identification number information assigned to each arithmetic processing circuit and cyclic number information assigned to each group, and a transmitting circuit that transmits the respective first data blocks selected by the data selecting circuit to the respective arithmetic processing
    Type: Application
    Filed: October 30, 2018
    Publication date: May 9, 2019
    Applicant: FUJITSU LIMITED
    Inventor: Akihiko Kasagi
  • Publication number: 20180246854
    Abstract: A computing method includes: generating first partitioned matrices by partitioning the first matrix by a least common multiple of the M and the N in the row direction and by the N in the column direction; generating second partitioned matrices by partitioning the second matrix by the M in the row direction and by the least common multiple in the column direction; adding a first product of the first partitioned matrices and the second partitioned matrices to a first result matrix; transmitting the first partitioned matrices to computing elements directly connected to that computing element out of other computing elements connected to each other in a torus-like manner in the row direction; transmitting the second partitioned matrices to computing elements directly connected to that computing element out of other computing elements connected to each other in a torus-like manner in the column direction.
    Type: Application
    Filed: February 13, 2018
    Publication date: August 30, 2018
    Applicant: FUJITSU LIMITED
    Inventor: Akihiko Kasagi
  • Publication number: 20180150934
    Abstract: An information processing device includes a first memory and a processor. The processor includes a circuit and a second memory. The circuit calculates a first value from a plurality of third pixels that are located above an interpolation pixel from among a plurality of first pixels, calculates a second value from a plurality of fourth pixels that are located above the interpolation pixel from among an plurality of second pixels, calculates a third value from a plurality of fifth pixels that are located below the interpolation pixel, calculates a fourth value from a plurality of sixth pixels that are located below the interpolation pixel, calculates a first gradient value from the first and third values, calculates a second gradient value from the second and fourth values, determines an edge direction according to the first gradient value and the second gradient value, and calculates a pixel value of an interpolation pixel.
    Type: Application
    Filed: October 23, 2017
    Publication date: May 31, 2018
    Applicant: FUJITSU LIMITED
    Inventor: Akihiko Kasagi
  • Publication number: 20180032869
    Abstract: A machine learning method, using a neural network as a model, executed by a computer, the machine learning method including dividing a first batch data into a plurality of pieces of second batch data, the first batch data being a set of sample data to be input into the model in a machine learning, allocating the plurality of pieces of second batch data to a plurality of computers, the model having a specified layered structure and a specified parameter of the neural network being applied to the plurality of computers, making the plurality of computers to execute the machine learning based on the plurality of allocated second batch data, obtaining, from each of the plurality of computers, a plurality of correction amounts of the parameter derived by the executed machine learning, and correcting the model by modifying the specified parameter in accordance with the plurality of correction amounts.
    Type: Application
    Filed: July 27, 2017
    Publication date: February 1, 2018
    Applicant: FUJITSU LIMITED
    Inventors: Tsuguchika TABARU, Masafumi YAMAZAKI, Akihiko KASAGI
  • Publication number: 20180032911
    Abstract: The parallel information processing apparatus includes a plurality of nodes each including a first processor and a second processor. The first processor is configured to execute a computation process using a coefficient for a target data, computing a coefficient variation based on a result of the computation process, transferring the computed coefficient variation to the second processor and requesting the second processor to execute a transfer/receipt process. The second processor is configured to transmit the coefficient variation transferred from the first processor to another node and receive the coefficient variation computed by another node and integrate the coefficient variation transferred from the first processor and the coefficient variation computed by another node. At least one of the first processor and the second processor updates the coefficient to be used for the computation process from next time onward based on the integrated coefficient variation.
    Type: Application
    Filed: June 27, 2017
    Publication date: February 1, 2018
    Applicant: FUJITSU LIMITED
    Inventors: Masafumi Yamazaki, Tsuguchika TABARU, Akihiko Kasagi
  • Publication number: 20180005113
    Abstract: An information processing apparatus includes a pooling layer and a convolution layer. The pooling layer acquires, information on an error gradient including a plurality of elements from an upper layer. The convolution layer specifies, when computing a value of one element included in a weight gradient, an area corresponding to the one element among from a plurality of elements included information acquired from a lower layer, and divides the specified area having elements into a plurality of partial areas. The convolution layer computes, for each of the partial areas, a value based on one or more total values of the elements included in the one or more partial areas and a value of one of the elements of the error gradient corresponding to the corresponding partial area, and totalizes the computed values to execute a process for computing the value of the one element.
    Type: Application
    Filed: April 25, 2017
    Publication date: January 4, 2018
    Applicant: FUJITSU LIMITED
    Inventor: Akihiko Kasagi
  • Publication number: 20170371838
    Abstract: A processor of an information processing apparatus generates an extended image by adding pixels to outside of a target image. The processor generates an integral image. A value of each element of the integral image is a sum of pixel values of first pixels of the extended image. The first pixels are included in a direction toward an origin of the extended image from a pixel corresponding to the element of the integral image. The processor generates a partial-sum matrix for each pixel of a reduced image using the integral image. A value of each element of the partial-sum matrix is a sum of pixel values of second pixels of the extended image. The second pixels are included in an area corresponding to the element of the partial-sum matrix. The processor performs a convolution operation on the partial-sum matrix using the filter matrix.
    Type: Application
    Filed: May 30, 2017
    Publication date: December 28, 2017
    Applicant: FUJITSU LIMITED
    Inventor: Akihiko Kasagi
  • Patent number: 9600763
    Abstract: An computer-implemented information processing method for a convolutional neural network processing input data, includes: identifying, by a computer, for each of elements of a kernel used in convolution operation, input values to be multiplied by the respective elements in the convolution operation from among input values included in the input data; calculating a sum total of identified input values; calculating, for each of the elements of the kernel, a product of the sum total and the element; calculating an average of calculated products; and performing the convolution operation within the convolutional neural network based on the average of the calculated products.
    Type: Grant
    Filed: September 13, 2016
    Date of Patent: March 21, 2017
    Assignee: FUJITSU LIMITED
    Inventor: Akihiko Kasagi