Patents by Inventor Akihiko Kohno
Akihiko Kohno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8717340Abstract: Disclosed is a thin film transistor that is provided with a gate insulating film that is inexpensive, and that is less likely to have a low-density microcrystalline silicon layer formed thereon due to plasma induced damage, while suppressing fluctuation of a threshold voltage. In a TFT (100) having the bottom gate structure, since a silicon nitride film (31) having a natural oxide film (32) formed on the surface thereof is used as the gate insulating film (30), the gate insulating film (30) is not only capable of preventing the alkali metal ions contained in a glass substrate (10) from entering the gate insulating film (30), but also capable of suppressing a formation of the low-density microcrystalline silicon layer on the surface of a microcrystalline silicon film (41) on the side in contact with the gate insulating film (30). Since the mobility of the microcrystalline silicon film (41) is increased, the operation speed of the TFT (100) can be improved.Type: GrantFiled: October 20, 2010Date of Patent: May 6, 2014Assignee: Sharp Kabushiki KaishaInventors: Toshio Mizuki, Akihiko Kohno, Kohichi Tanaka
-
Publication number: 20130087802Abstract: It is an object to increase the mobility of a thin film transistor having an active layer including a microcrystalline semiconductor film. Upon fabricating an inverted staggered type TFT 10, a substrate is vacuum-transferred to a plasma enhanced CVD apparatus such that a surface of a microcrystalline silicon film (active layer 40) exposed by gap etching is not exposed to the air. An insulating film 80 is deposited by the plasma enhanced CVD apparatus so as to completely cover the exposed surface of the microcrystalline silicon film. By this, even if the microcrystalline silicon film is exposed to the air, oxygen cannot be adsorbed on the surface thereof and thus diffusion of oxygen into the microcrystalline silicon film can be suppressed. In addition, since N+ silicon films composing contact layers 50a and 50b directly contact with the microcrystalline silicon film, the contact resistance can be reduced.Type: ApplicationFiled: March 25, 2011Publication date: April 11, 2013Inventors: Akihiko Kohno, Toshio Mizuki, Kohichi Tanaka
-
Patent number: 8378348Abstract: A semiconductor device 101 includes: a substrate 1; an active layer 4 provided on the substrate 1 and including a channel region 4c, and a first region 4a and a second region 4b that are respectively located on opposite sides of the channel region 4c; first and second contact layers 6a and 6b respectively in contact with the first and second regions 4a and 4b of the active layer 4; a first electrode 7 electrically coupled to the first region 4a via the first contact layer 6a; a second electrode 8 electrically coupled to the second region 4b via the second contact layer 6b; and a gate electrode 2 provided such that a gate insulating layer 3 is interposed between the gate electrode 2 and the active layer 4, the gate electrode 2 being configured to control a conductivity of the channel region 4c. The active layer 4 contains silicon. The semiconductor device further includes an oxygen-containing silicon layer 5 between the active layer 4 and the first and second contact layers 6a, 6b.Type: GrantFiled: January 8, 2009Date of Patent: February 19, 2013Assignee: Sharp Kabushiki KaishaInventors: Yuichi Saito, Masao Moriguchi, Akihiko Kohno
-
Publication number: 20120287094Abstract: Disclosed is a thin film transistor that is provided with a gate insulating film that is inexpensive, and that is less likely to have a low-density microcrystalline silicon layer formed thereon due to plasma induced damage, while suppressing fluctuation of a threshold voltage. In a TFT (100) having the bottom gate structure, since a silicon nitride film (31) having a natural oxide film (32) formed on the surface thereof is used as the gate insulating film (30), the gate insulating film (30) is not only capable of preventing the alkali metal ions contained in a glass substrate (10) from entering the gate insulating film (30), but also capable of suppressing a formation of the low-density microcrystalline silicon layer on the surface of a microcrystalline silicon film (41) on the side in contact with the gate insulating film (30). Since the mobility of the microcrystalline silicon film (41) is increased, the operation speed of the TFT (100) can be improved.Type: ApplicationFiled: October 20, 2010Publication date: November 15, 2012Applicant: SHARP KABUSHIKI KAISHAInventors: Toshio Mizuki, Akihiko Kohno, Kohichi Tanaka
-
Publication number: 20120216828Abstract: Disclosed is a substrate cleaning device provided with: a generation unit that generates ozone micro-nanobubble water; a nozzle header unit provided with a plurality of spray nozzles that spray the ozone micro-nanobubble water; and a substrate support unit that supports a substrate to be treated. The surface of the substrate supported by the substrate support unit is cleaned by spraying the ozone micro-nanobubble water from the plurality of spray nozzles onto the substrate.Type: ApplicationFiled: May 17, 2010Publication date: August 30, 2012Applicant: SHARP KABUSHIKI KAISHAInventors: Junichi Tanaka, Akihiko Kohno
-
Publication number: 20120193633Abstract: A method for fabricating a semiconductor device according to the present invention includes the steps of: (a) providing a substrate (11a) in a chamber (26); (b) supplying a microwave into the chamber (26) through a dielectric plate (24), of which one surface that faces the chamber is made of alumina, thereby depositing a microcrystalline silicon film (14) with an aluminum concentration of 1.0×1016 atoms/cm3 or less on the substrate (11a) by high-density plasma CVD process; and (c) making a thin-film transistor that uses the microcrystalline silicon film as its active layer. As a result, a semiconductor device including a TFT that uses a microcrystalline silicon film with a mobility of more than 0.5 cm2/Vs as its active layer is obtained.Type: ApplicationFiled: September 21, 2010Publication date: August 2, 2012Applicant: SHARP KABUSHIKI KAISHAInventors: Akihiko Kohno, Toshio Mizuki, Kohichi Tanaka
-
Publication number: 20120104403Abstract: An object of the present invention is to provide a thin film transistor having a gate insulating film for suppressing a shift amount of a threshold voltage generated by use under a high temperature environment. In a thin film transistor having a channel layer made of microcrystalline silicon, a gate insulating film 140 is a film obtained by laminating a first silicon nitride film 141 having a nitrogen concentration of 6×1021 atoms/cc or less and a second silicon nitride film 142 having a nitrogen concentration higher than 6×1021 atoms/cc. Therefore, the second silicon nitride film 142 increases the blocking effect against mobile ions entering from a glass substrate 20 to make the mobile ions less likely to be stored in an interface with a channel layer 50. The first silicon nitride film 141 increases the dielectric breakdown voltage of the gate insulating film 140.Type: ApplicationFiled: February 22, 2010Publication date: May 3, 2012Applicant: SHARP KABUSHIKI KAISHAInventors: Akihiko Kohno, Masao Moriguchi, Yuhichi Saitoh
-
Publication number: 20100295047Abstract: To provide a semiconductor device which achieves a high ON current and a low OFF current at the same time, and a fabrication method thereof. A semiconductor device of the present invention includes a glass substrate 1, an island-shaped semiconductor layer 4 which includes a first region 4c, a second region 4a, and a third region 4c, a source region 5a and a drain region 5b, a source electrode 6a, a drain electrode 6b, and a gate electrode 2 for controlling the conductivity of the first region 4c. The upper surface of the first region 4c is closer to the glass substrate 1 than the upper surfaces of ends of the second region 4a and the third region 4b adjacent to the first region 4c are. The distances between the upper surfaces of the ends of the second region 4a and the third region 4b and the upper surface of the first region 4c along the thickness direction of the semiconductor layer 4 are each independently not less than one time and not more than seven times the thickness of the first region 4b.Type: ApplicationFiled: January 23, 2009Publication date: November 25, 2010Inventors: Masao Moriguchi, Yuichi Saito, Akihiko Kohno