Patents by Inventor Akihiko Konmoto

Akihiko Konmoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor integrated circuit
    Patent number: 7734433
    Abstract: A semiconductor integrated circuit includes a first power source having a power supply voltage that operates the semiconductor integrated circuit, a voltage comparator that compares the power supply voltage with a reference voltage, and a comparison result recording unit that records a comparison result of the voltage comparator, wherein the comparison result recording unit records a length of a period based on a clock signal for which the power supply voltage exceeds the reference voltage.
    Type: Grant
    Filed: January 17, 2008
    Date of Patent: June 8, 2010
    Assignee: Fujitsu Limited
    Inventor: Akihiko Konmoto
  • Semiconductor Intergrated Circuit
    Publication number: 20080191747
    Abstract: A semiconductor integrated circuit includes a first power source having a power supply voltage that operates the semiconductor integrated circuit, a voltage comparator that compares the power supply voltage with a reference voltage, and a comparison result recording unit that records a comparison result of the voltage comparator, wherein the comparison result recording unit records a length of a period based on a clock signal for which the power supply voltage exceeds the reference voltage.
    Type: Application
    Filed: January 17, 2008
    Publication date: August 14, 2008
    Applicant: FUJITSU LIMITED
    Inventor: Akihiko KONMOTO
  • Integrated circuit
    Publication number: 20080042714
    Abstract: An integrated circuit includes a first latch of a data transmitting source and a second latch of a data receiving destination. The second latch includes: a delay element that delays an input signal transmitted from the first latch; and a path switching circuit that changes over a signal input path in such a way that at time of a usual operation, the input signal is taken through bypassing the delay element and at time of a test operation, the input signal is taken via the delay element.
    Type: Application
    Filed: October 10, 2006
    Publication date: February 21, 2008
    Applicant: FUJITSU LIMITED
    Inventors: Takashi Otake, Akihiko Konmoto