Patents by Inventor Akihiko Miyanohara
Akihiko Miyanohara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240073560Abstract: To control an excess bias to an appropriate value in a light detection device. A solid-state image sensor includes a photodiode, a resistor, and a control circuit. In this solid-state image sensor, the photodiode photoelectrically converts incident light and outputs a photocurrent. Furthermore, in the solid-state image sensor, the resistor is connected to a cathode of the photodiode. Furthermore, in the solid-state image sensor, the control circuit supplies a lower potential to an anode of the photodiode as a potential of the cathode of when the photocurrent flows through the resistor is higher.Type: ApplicationFiled: October 12, 2023Publication date: February 29, 2024Inventors: Tatsuki Nishino, Hiroki Hiyama, Shizunori Matsumoto, Takahiro Miura, Akihiko Miyanohara, Tomohiro Matsumoto
-
Patent number: 11818481Abstract: To control an excess bias to an appropriate value in a light detection device. A solid-state image sensor includes a photodiode, a resistor, and a control circuit. In this solid-state image sensor, the photodiode photoelectrically converts incident light and outputs a photocurrent. Furthermore, in the solid-state image sensor, the resistor is connected to a cathode of the photodiode. Furthermore, in the solid-state image sensor, the control circuit supplies a lower potential to an anode of the photodiode as a potential of the cathode of when the photocurrent flows through the resistor is higher.Type: GrantFiled: November 15, 2022Date of Patent: November 14, 2023Assignee: Sony Semiconductor Solutions CorporationInventors: Tatsuki Nishino, Hiroki Hiyama, Shizunori Matsumoto, Takahiro Miura, Akihiko Miyanohara, Tomohiro Matsumoto
-
Publication number: 20230124216Abstract: In a sensing device that generates a distance image, a variation in distance measurement accuracy in the distance image is reduced. The sensing device includes a predetermined number of pixel circuits and a voltage control unit. Each of the predetermined number of pixel circuits includes a photoelectric conversion element and a detection circuit. A predetermined reverse bias voltage is applied between an anode and a cathode of the photoelectric conversion element. The detection circuit detects whether a photon is present or absent on the basis of a potential of either the anode or the cathode. The voltage control unit adjusts the reverse bias voltage to a value corresponding to a breakdown voltage of the photoelectric conversion element for each of the pixel circuits.Type: ApplicationFiled: December 21, 2020Publication date: April 20, 2023Inventors: AKIHIKO MIYANOHARA, HIROKI HIYAMA
-
Publication number: 20230086897Abstract: To control an excess bias to an appropriate value in a light detection device. A solid-state image sensor includes a photodiode, a resistor, and a control circuit. In this solid-state image sensor, the photodiode photoelectrically converts incident light and outputs a photocurrent. Furthermore, in the solid-state image sensor, the resistor is connected to a cathode of the photodiode. Furthermore, in the solid-state image sensor, the control circuit supplies a lower potential to an anode of the photodiode as a potential of the cathode of when the photocurrent flows through the resistor is higher.Type: ApplicationFiled: November 15, 2022Publication date: March 23, 2023Inventors: Tatsuki Nishino, Hiroki Hiyama, Shizunori Matsumoto, Takahiro Miura, Akihiko Miyanohara, Tomohiro Matsumoto
-
Patent number: 11533445Abstract: To control an excess bias to an appropriate value in a light detection device. A solid-state image sensor includes a photodiode, a resistor, and a control circuit. In this solid-state image sensor, the photodiode photoelectrically converts incident light and outputs a photocurrent. Furthermore, in the solid-state image sensor, the resistor is connected to a cathode of the photodiode. Furthermore, in the solid-state image sensor, the control circuit supplies a lower potential to an anode of the photodiode as a potential of the cathode of when the photocurrent flows through the resistor is higher.Type: GrantFiled: August 24, 2018Date of Patent: December 20, 2022Assignee: Sony Semiconductor Solutions CorporationInventors: Tatsuki Nishino, Hiroki Hiyama, Shizunori Matsumoto, Takahiro Miura, Akihiko Miyanohara, Tomohiro Matsumoto
-
Publication number: 20220345652Abstract: In a solid-state imaging element that measures a distance, miniaturization of pixels is facilitated. The solid-state imaging element includes a pixel array unit and a photon number detection unit. In the solid-state imaging element including the pixel array unit and the photon number detection unit, the pixel array unit is provided with a plurality of pixels that generates a predetermined analog signal depending on incidence of a photon and a signal line to which the plurality of pixels is connected in common. Furthermore, in the solid-state imaging element, the photon number detection unit detects the number of photons incident, on the basis of the analog signal transmitted via the signal line.Type: ApplicationFiled: July 13, 2020Publication date: October 27, 2022Inventors: MASAMUNE HAMAMATSU, AKIHIKO MIYANOHARA
-
Publication number: 20220291342Abstract: Proposed is a ranging system capable of improving the accuracy of ranging. A ranging system (70) includes: a drive unit (24) that causes a light emitting element to emit light and outputs a drive signal for irradiating a target with light; a sensor unit (302) that detects reflected light from the target; a measurement unit (23) that measures a delay time that is included in a time from timing at which a trigger signal for causing the light emitting element to emit light is output to timing at which the light emitting element actually emits light; and a ranging observation unit (52) which is a processing unit that performs a process of calculating a distance to the target on the basis of output timing of the trigger signal, light receiving timing of the reflected light obtained by the sensor unit, and the delay time.Type: ApplicationFiled: August 27, 2020Publication date: September 15, 2022Inventors: Daisuke Suzuki, Takashi Masuda, Mitsushi Tabata, Kouta Hiyama, Koichi Okamoto, Akihiko Miyanohara
-
Publication number: 20200314375Abstract: To control an excess bias to an appropriate value in a light detection device. A solid-state image sensor includes a photodiode, a resistor, and a control circuit. In this solid-state image sensor, the photodiode photoelectrically converts incident light and outputs a photocurrent. Furthermore, in the solid-state image sensor, the resistor is connected to a cathode of the photodiode. Furthermore, in the solid-state image sensor, the control circuit supplies a lower potential to an anode of the photodiode as a potential of the cathode of when the photocurrent flows through the resistor is higher.Type: ApplicationFiled: August 24, 2018Publication date: October 1, 2020Inventors: Tatsuki Nishino, Hiroki Hiyama, Shizunori Matsumoto, Takahiro Miura, Akihiko Miyanohara, Tomohiro Matsumoto
-
Patent number: 9025062Abstract: A solid-state imaging device includes a pixel array unit having a plurality of pixels arranged in a matrix form which perform a photoelectric conversion, a pixel signal readout unit having a logic unit and performing a readout of a pixel signal from the pixel array unit, a regulator, a first circuit section, a second circuit section, and a stacked structure in which the first and second circuit sections are bonded, wherein the first circuit section has the pixel array unit disposed therein, and wherein the second circuit section has at least the logic unit and the regulator disposed therein, wherein the regulator includes a reference voltage generation, a plurality of output stage transistors, and an operational amplifier comparing the reference voltage and a commonized output voltage, and an output path of the output stage transistors are connected to a single node, and then is fed back to the operational amplifier.Type: GrantFiled: May 20, 2014Date of Patent: May 5, 2015Assignee: Sony CorporationInventors: Shimon Teshima, Kenichi Shigenami, Akihiko Miyanohara, Shoji Kobayashi
-
Publication number: 20140253770Abstract: A solid-state imaging device includes a pixel array unit having a plurality of pixels arranged in a matrix form which perform a photoelectric conversion, a pixel signal readout unit having a logic unit and performing a readout of a pixel signal from the pixel array unit, a regulator, a first circuit section, a second circuit section, and a stacked structure in which the first and second circuit sections are bonded, wherein the first circuit section has the pixel array unit disposed therein, and wherein the second circuit section has at least the logic unit and the regulator disposed therein, wherein the regulator includes a reference voltage generation, a plurality of output stage transistors, and an operational amplifier comparing the reference voltage and a commonized output voltage, and an output path of the output stage transistors are connected to a single node, and then is fed back to the operational amplifier.Type: ApplicationFiled: May 20, 2014Publication date: September 11, 2014Applicant: Sony CorporationInventors: Shimon Teshima, Kenichi Shigenami, Akihiko Miyanohara, Shoji Kobayashi
-
Patent number: 8767107Abstract: A solid-state imaging device includes a pixel array unit having a plurality of pixels arranged in a matrix form which perform a photoelectric conversion, a pixel signal readout unit having a logic unit and performing a readout of a pixel signal from the pixel array unit, a regulator, a first chip, a second chip, and a stacked structure in which both the first chip and the second chip are bonded, wherein the first chip has the pixel array unit disposed therein, and wherein the second chip has at least the logic unit and the regulator disposed therein, wherein the regulator includes a reference voltage generation, a plurality of output stage transistors, and an operational amplifier comparing the reference voltage and a commonized output voltage, and an output path of the output stage transistors are connected to a single node, and then is fed back to the operational amplifier.Type: GrantFiled: October 22, 2012Date of Patent: July 1, 2014Assignee: Sony CorporationInventors: Shimon Teshima, Kenichi Shigenami, Akihiko Miyanohara, Shoji Kobayashi
-
Patent number: 7205736Abstract: Methods and systems for driving a motor are disclosed. A center tap voltage and a desired center tap voltage are used to generate a voltage feedback. A power amplifier receives a reference current and the voltage feedback. The power amplifier provides a phase current to a phase of a motor. The phase current is substantially centered about the desired center tap voltage as a consequence of the voltage feedback. Thus, high-side to low-side or state to state current variations are reduced thereby reducing the occurrence of problems such as torque ripple and back EMF.Type: GrantFiled: April 2, 2003Date of Patent: April 17, 2007Assignee: Texas Instruments IncorporatedInventors: Jonathan R. Knight, Akihiko Miyanohara
-
Publication number: 20060108955Abstract: Methods and systems for driving a motor are disclosed. A center tap voltage and a desired center tap voltage are used to generate a voltage feedback. A power amplifier receives a reference current and the voltage feedback. The power amplifier provides a phase current to a phase of a motor. The phase current is substantially centered about the desired center tap voltage as a consequence of the voltage feedback. Thus, high-side to low-side or state to state current variations are reduced thereby reducing the occurrence of problems such as torque ripple and back EMF.Type: ApplicationFiled: April 2, 2003Publication date: May 25, 2006Inventors: Jonathan Knight, Akihiko Miyanohara
-
Patent number: 6778005Abstract: The present invention improves on the topology of a conventional current source by interposing an RC circuit and additional MOS between the output of a buffer and the output of the current source. The topology of the present invention advantageously provides a clean current output by shunting noise to ground.Type: GrantFiled: December 27, 2002Date of Patent: August 17, 2004Assignee: Texas Instruments IncorporatedInventors: Futoshi Fujiwara, Akihiko Miyanohara
-
Publication number: 20030169099Abstract: The present invention improves on the topology of a conventional current source by interposing an RC circuit and additional MOS between the output of a buffer and the output of the current source. The topology of the present invention advantageously provides a clean current output by shunting noise to ground.Type: ApplicationFiled: December 27, 2002Publication date: September 11, 2003Inventors: Futoshi Fujiwara, Akihiko Miyanohara