Patents by Inventor Akihiko Nogi

Akihiko Nogi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Direct current voltage output circuit and set top box
    Patent number: 8884686
    Abstract: When the conduction state of at least one MOS transistor of a PMOS transistor (P1) and NMOS transistor (N2) is switched to an off state, current which would be applied to the MOS transistor with a conduction state in the off state due to the conduction state becoming the off state is bypassed to a resistor (R3, R4). Due to this, an MOS transistor with a conduction state in the off state being supplied with direct current power as it is can be avoided and the withstand voltage of that MOS transistor does not have to be raised. For this reason, the manufacturing costs of the direct current voltage output circuit (54a) can be kept down. At the same time, the circuit size of the direct current voltage output circuit (54a) can be made smaller.
    Type: Grant
    Filed: July 4, 2012
    Date of Patent: November 11, 2014
    Assignee: Asahi Kasei Microdevices Corporation
    Inventor: Akihiko Nogi
  • DIRECT CURRENT VOLTAGE OUTPUT CIRCUIT AND SET TOP BOX
    Publication number: 20130145416
    Abstract: When the conduction state of at least one MOS transistor of a PMOS transistor (P1) and NMOS transistor (N2) is switched to an off state, current which would be applied to the MOS transistor with a conduction state in the off state due to the conduction state becoming the off state is bypassed to a resistor (R3, R4). Due to this, an MOS transistor with a conduction state in the off state being supplied with direct current power as it is can be avoided and the withstand voltage of that MOS transistor does not have to be raised. For this reason, the manufacturing costs of the direct current voltage output circuit (54a) can be kept down. At the same time, the circuit size of the direct current voltage output circuit (54a) can be made smaller.
    Type: Application
    Filed: July 4, 2012
    Publication date: June 6, 2013
    Applicant: ASAHI KASEI MICRODEVICES CORPORATION
    Inventor: Akihiko Nogi
  • Mute circuit
    Patent number: 6734746
    Abstract: To provide a mute circuit capable of reducing or eliminating noises generated in accordance with an offset voltage under a mute operation. The present invention comprises a summing amplifier, switch, and mute signal generating circuit.
    Type: Grant
    Filed: January 2, 2003
    Date of Patent: May 11, 2004
    Assignee: Asahi Kasei Microsystems Co., Ltd.
    Inventor: Akihiko Nogi