Patents by Inventor Akihiko Ohi

Akihiko Ohi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200249185
    Abstract: The present invention is to provide a small-sized dryness/wetness responsive sensor that detects a galvanic current with a high sensitivity as a principle of operation. According to one embodiment of the present invention, a dryness/wetness responsive sensor comprises a thin wire made of a first metal and a thin wire made of a second metal, the second metal is different from the first metal, the thin wire of the first metal and the thin wire of the second metal are disposed in juxtaposition with each other on an insulating substrate, and a surface state of a part between the thin wire of the first metal and the thin wire of the second metal is hydrophilic or hydrophobic.
    Type: Application
    Filed: August 23, 2018
    Publication date: August 6, 2020
    Applicant: NATIONAL INSTITUTE FOR MATERIALS SCIENCE
    Inventors: Jin KAWAKITA, Akihiko OHI, Tomoko OHKI, Naoki IKEDA, Toshihide NABATAME, Toyohiro CHIKYO
  • Publication number: 20190145920
    Abstract: The present invention improves the sensitivity and the responsiveness of a dryness/wetness responsive sensor utilizing a galvanic current, allowing for downsizing of the dryness/wetness responsive sensor. Instead of the conventional structure in which an anode electrode and a cathode electrode are stacked with an intervening insulator, the present invention employs a structure in which both electrodes run in juxtaposition with each other on an insulating substrate in the form of, for example, a comb-shaped electrode as shown in the drawing. By utilizing a semiconductor manufacturing process or any other micro/nano-fabrication technology, an inter-electrode distance can be extremely shortened as compared with the conventional sensors, allowing enhancing the sensitivity per unit footprint of the electrodes. Accordingly, a decrease in the size of the dryness/wetness responsive sensor can be easily achieved.
    Type: Application
    Filed: December 19, 2018
    Publication date: May 16, 2019
    Applicant: NATIONAL INSTITUTE FOR MATERIALS SCIENCE
    Inventors: Jin KAWAKITA, Tadashi SHINOHARA, Toyohiro CHIKYO, Toshihide NABATAME, Akihiko OHI, Tomoko OHKI
  • Patent number: 10267756
    Abstract: A dryness/wetness responsive sensor having decreased size, and improved sensitivity and responsiveness. The present invention comprises a thin wire of a first metal and a thin wire of a second metal, which is different from the first metal, wherein the thin wires run in juxtaposition with each other on an insulating substrate, and wherein the spacing between the first thin wire and the second thin wire is in the range of 5 nm or more and less than 20 ?m.
    Type: Grant
    Filed: July 21, 2015
    Date of Patent: April 23, 2019
    Assignee: NATIONAL INSTITUTE FOR MATERIALS SCIENCE
    Inventors: Jin Kawakita, Tadashi Shinohara, Toyohiro Chikyo, Toshihide Nabatame, Akihiko Ohi, Tomoko Ohki
  • Patent number: 9818845
    Abstract: A mask used to form an n+ source layer (11) is formed by a nitride film on the surface of a substrate before a trench (7) is formed. At this time, a sufficient width of the n+ source layer (11) on the surface of the substrate is secured. Thereby, stable contact between the n+ source layer (11) and a source electrode (15) is obtained. A CVD oxide film (12) that is an interlayer insulating film having a thickness of 0.1 micrometer or more and 0.3 micrometer or less is formed on doped poly-silicon to be used as a gate electrode (10a) embedded in the trench (7), and non-doped poly-silicon (13) that is not oxidized is formed on the CVD oxide film (12). Thereby, generation of void in the CVD oxide film (12) is suppressed and, by not oxidizing the non-doped poly-silicon (13), a semiconductor apparatus is easily manufactured.
    Type: Grant
    Filed: December 13, 2016
    Date of Patent: November 14, 2017
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Kin-On Sin, Chun-Wai Ng, Hitoshi Sumida, Yoshiaki Toyada, Akihiko Ohi, Hiroyuki Tanaka, Takeyoshi Nishimura
  • Publication number: 20170167995
    Abstract: The present invention improves the sensitivity and the responsiveness of a dryness/wetness responsive sensor utilizing a galvanic current, allowing for downsizing of the dryness/wetness responsive sensor. Instead of the conventional structure in which an anode electrode and a cathode electrode are stacked with an intervening insulator, the present invention employs a structure in which both electrodes run in juxtaposition with each other on an insulating substrate in the form of, for example, a comb-shaped electrode as shown in the drawing. By utilizing a semiconductor manufacturing process or any other micro/nano-fabrication technology, an inter-electrode distance can be extremely shortened as compared with the conventional sensors, allowing enhancing the sensitivity per unit footprint of the electrodes. Accordingly, a decrease in the size of the dryness/wetness responsive sensor can be easily achieved.
    Type: Application
    Filed: July 21, 2015
    Publication date: June 15, 2017
    Applicant: NATIONAL INSTITUTE FOR MATERIALS SCIENCE
    Inventors: Jin KAWAKITA, Tadashi SHINOHARA, Toyohiro CHIKYO, Toshihide NABATAME, Akihiko OHI, Tomoko OHKI
  • Publication number: 20170092744
    Abstract: A mask used to form an n+ source layer (11) is formed by a nitride film on the surface of a substrate before a trench (7) is formed. At this time, a sufficient width of the n+ source layer (11) on the surface of the substrate is secured. Thereby, stable contact between the n+ source layer (11) and a source electrode (15) is obtained. A CVD oxide film (12) that is an interlayer insulating film having a thickness of 0.1 micrometer or more and 0.3 micrometer or less is formed on doped poly-silicon to be used as a gate electrode (10a) embedded in the trench (7), and non-doped poly-silicon (13) that is not oxidized is formed on the CVD oxide film (12). Thereby, generation of void in the CVD oxide film (12) is suppressed and, by not oxidizing the non-doped poly-silicon (13), a semiconductor apparatus is easily manufactured.
    Type: Application
    Filed: December 13, 2016
    Publication date: March 30, 2017
    Inventors: Kin-On SIN, Chun-Wai NG, Hitoshi SUMIDA, Yoshiaki TOYADA, Akihiko OHI, Hiroyuki TANAKA, Takeyoshi NISHIMURA
  • Patent number: 9553185
    Abstract: A mask used to form an n+ source layer (11) is formed by a nitride film on the surface of a substrate before a trench (7) is formed. At this time, a sufficient width of the n+ source layer (11) on the surface of the substrate is secured. Thereby, stable contact between the n+ source layer (11) and a source electrode (15) is obtained. A CVD oxide film (12) that is an interlayer insulating film having a thickness of 0.1 micrometer or more and 0.3 micrometer or less is formed on doped poly-silicon to be used as a gate electrode (10a) embedded in the trench (7), and non-doped poly-silicon (13) that is not oxidized is formed on the CVD oxide film (12). Thereby, generation of void in the CVD oxide film (12) is suppressed and, by not oxidizing the non-doped poly-silicon (13), a semiconductor apparatus is easily manufactured.
    Type: Grant
    Filed: May 27, 2010
    Date of Patent: January 24, 2017
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Kin-On Sin, Chun-Wai Ng, Hitoshi Sumida, Yoshiaki Toyada, Akihiko Ohi, Hiroyuki Tanaka, Takeyoshi Nishimura
  • Patent number: 9222970
    Abstract: A fault position analysis method and a fault position analysis device for a semiconductor device, through which a fault position of a SiC semiconductor device can be analyzed and specified by an OBIRCH method, are disclosed. The fault position analysis method for the semiconductor device scans and irradiates a device and a circuit on a front surface of a substrate with a laser beam from a rear surface side of the substrate of the semiconductor device to heat the device and the circuit. It causes a current to flow to the device and the circuit while being heated, detects a change in a resistance value caused by a change in a current, and analyzes the fault position. The semiconductor device is a semiconductor device which uses an N-doped SiC substrate. Laser beams having wavelengths of 650 to 810 nm are used.
    Type: Grant
    Filed: November 8, 2012
    Date of Patent: December 29, 2015
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Katsunori Suzuki, Akihiko Ohi, Shoji Kitamura, Takahiro Ooyama
  • Patent number: 8399340
    Abstract: A method of manufacturing a super-junction semiconductor device facilitates increasing the epitaxial growth rate without increasing the manufacturing steps greatly. In substitution for the formation of alignment mark in the surfaces of the second and subsequent non-doped epitaxial layers, patterning for forming a new alignment mark is conducted simultaneously with the resist pattering for selective ion-implantation into the second and subsequent non-doped epitaxial layers in order to form the new alignment mark at a position different from the position, at which the initial alignment mark is formed, and to form the new alignment mark in every one or more repeated epitaxial layer growth cycles.
    Type: Grant
    Filed: June 10, 2011
    Date of Patent: March 19, 2013
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Akihiko Ohi
  • Publication number: 20130001681
    Abstract: A mask used to form an n+ source layer (11) is formed by a nitride film on the surface of a substrate before a trench (7) is formed. At this time, a sufficient width of the n+ source layer (11) on the surface of the substrate is secured. Thereby, stable contact between the n+ source layer (11) and a source electrode (15) is obtained. A CVD oxide film (12) that is an interlayer insulating film having a thickness of 0.1 micrometer or more and 0.3 micrometer or less is formed on doped poly-silicon to be used as a gate electrode (10a) embedded in the trench (7), and non-doped poly-silicon (13) that is not oxidized is formed on the CVD oxide film (12). Thereby, generation of void in the CVD oxide film (12) is suppressed and, by not oxidizing the non-doped poly-silicon (13), a semiconductor apparatus is easily manufactured.
    Type: Application
    Filed: May 27, 2010
    Publication date: January 3, 2013
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Kin-On Sin, Chun-Wai Ng, Hitoshi Sumida, Yoshiaki Toyada, Akihiko Ohi, Hiroyuki Tanaka, Takeyoshi Nishimura
  • Publication number: 20110306191
    Abstract: A method of manufacturing a super-junction semiconductor device facilitates increasing the epitaxial growth rate without increasing the manufacturing steps greatly. In substitution for the formation of alignment mark in the surfaces of the second and subsequent non-doped epitaxial layers, patterning for forming a new alignment mark is conducted simultaneously with the resist pattering for selective ion-implantation into the second and subsequent non-doped epitaxial layers in order to form the new alignment mark at a position different from the position, at which the initial alignment mark is formed, and to form the new alignment mark in every one or more repeated epitaxial layer growth cycles.
    Type: Application
    Filed: June 10, 2011
    Publication date: December 15, 2011
    Applicant: FUJI ELECTRONIC CO., LTD.
    Inventor: Akihiko OHI
  • Patent number: 7510975
    Abstract: In the method for manufacturing a semiconductor device according to the invention including the step of forming trenches having the depth thereof in perpendicular to the major surface of a semiconductor substrate, the step of forming trenches includes the steps of performing trench etching using an insulator film, formed on the major surface of the semiconductor substrate and shaped with a predetermined pattern, for a mask to form the trenches; etching the inside of the trenches using a halogen containing gas to smoothen the inside of the trenches; and thermally treating in a non-oxidizing and non-nitriding atmosphere. The manufacturing method according to the invention facilitates well removing the etching residues remaining in the trenches and rounding the trench corners properly when the trenches are 2 ?m or narrower in width and even when the trenches are 1 ?m or narrower in width.
    Type: Grant
    Filed: September 23, 2005
    Date of Patent: March 31, 2009
    Assignee: Fuji Electric Holdings Co., Ltd.
    Inventors: Daisuke Kishimoto, Hitoshi Kuribayashi, Yuji Sano, Akihiko Ohi, Yoshihiko Nagayasu
  • Publication number: 20060154438
    Abstract: In the method for manufacturing a semiconductor device according to the invention including the step of forming trenches having the depth thereof in perpendicular to the major surface of a semiconductor substrate, the step of forming trenches includes the steps of performing trench etching using an insulator film, formed on the major surface of the semiconductor substrate and shaped with a predetermined pattern, for a mask to form the trenches; etching the inside of the trenches using a halogen containing gas to smoothen the inside of the trenches; and thermally treating in a non-oxidizing and non-nitriding atmosphere. The manufacturing method according to the invention facilitates well removing the etching residues remaining in the trenches and rounding the trench corners properly when the trenches are 2 ?m or narrower in width and even when the trenches are 1 ?m or narrower in width.
    Type: Application
    Filed: September 23, 2005
    Publication date: July 13, 2006
    Inventors: Daisuke Kishimoto, Hitoshi Kuribayashi, Yuji Sano, Akihiko Ohi, Yoshihiko Nagayasu
  • Patent number: 5441926
    Abstract: A superconducting transistor having a source region and a drain region are formed by a YBCO film on a barrier layer, which is composed of a PBCO film formed on an STO substrate. A gate electrode is disposed on the thinner wall at the back of the STO substrate. In a superconducting transistor so constructed the electric field created by the gate voltage works effectively at an interface with the barrier layer, more carriers can be drawn out relative to the applied gate voltage, and it becomes possible for a large superconduction current to flow.
    Type: Grant
    Filed: November 12, 1993
    Date of Patent: August 15, 1995
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Hiroshi Kimura, Toshiyuki Matsui, Takeshi Suzuki, Kazuo Mukae, Akihiko Ohi
  • Patent number: 5422336
    Abstract: A superconducting transistor with superior withstand voltage having source region and a drain region formed of oxide superconductors 3, a PrBa.sub.2 Cu.sub.3 O.sub.7-x layer 2 or an ScBa.sub.2 Cu.sub.3 O.sub.7-x layer 2 forming an intermediate region sandwiched by the source and drain regions. The regions are disposed on a substrate 1. An insulation layer 4 is disposed on the intermediate region. A transistor uses the intermediate region as an insulator when the gate is turned off, and as a superconductor when the gate is turned on.
    Type: Grant
    Filed: September 22, 1993
    Date of Patent: June 6, 1995
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Koichi Tsuda, Toshiyuki Matsui, Takeshi Suzuki, Hiroshi Kimura, Takashi Ishii, Akihiko Ohi, Kazuo Mukae
  • Patent number: 5275792
    Abstract: A nitrogen oxides-containing gas is contacted with a solid catalyst in the presence of methyl tert-butyl ether as a reducing agent for the conversion of the nitrogen oxides into molecular nitrogen. A supported catalyst including an alumina carrier having Pt, Rh or Ru supported thereon is desirably used as the solid catalyst.
    Type: Grant
    Filed: November 18, 1992
    Date of Patent: January 4, 1994
    Assignee: Agency of Industrial Science and Technology
    Inventors: Akira Obuchi, Atsushi Ogata, Koichi Mizuno, Akihiko Ohi, Hideo Ohuchi
  • Patent number: 5154901
    Abstract: An exhaust gas cleaner comprising a catalyst carried on a heat-resistant ter, the catalyst comprising (a) one or more alkali metals, (b) one or more metals selected from the group consisting of Zn, Sn and transition metals excluding platinum-group metals, and (c) one or more rare earth metals, and a method of cleaning an exhaust gas with it. Alkali metals may be added to a fuel.
    Type: Grant
    Filed: September 6, 1991
    Date of Patent: October 13, 1992
    Assignees: Kabushiki Kaisha Riken, Kozo Izuka Director-General of Agency of Industrial Science & Technology
    Inventors: Kiyohide Yoshida, Satoshi Sumiya, Takashi Ibusuki, Akira Obuchi, Hyogoro Aoyama, Akihiko Ohi, Hideo Ohuchi
  • Patent number: 5141714
    Abstract: An exhaust gas cleaner comprising (a) at least one filter made of a heat-resistant and electrically insulating material for trapping floating fine particles in an exhaust gas; and (b) at least a pair of electrodes stacked with the filter alternately, voltage being applied between the adjacent electrodes to burn electrically conductive and burnable fine particles trapped in the filter by heat generated by a current flowing between the adjacent electrodes, and the direction of the flow of the exhaust gas in the filter being essentially parallel to that of the laminate surface of the electrodes. The filter may carry a catalyst which functions to reduce harmful gas components in the exhaust gas.
    Type: Grant
    Filed: July 31, 1990
    Date of Patent: August 25, 1992
    Assignee: Kabushiki Kaisha Riken
    Inventors: Akira Obuchi, Hidenori Yoshiyama, Akihiko Ohi, Hyogoro Aoyama, Hideo Ohuchi, Atsushi Ogata, Koichi Mizuno, Seiji Makino, Kiyohide Yoshida, Gyo Muramatsu, Nobuyuki Matsumura, Satoshi Sumiya, Yoshikazu Takahashi