Abstract: In a semiconductor device having a Low-k film as an interlayer insulator, peeling of the interlayer insulator in a thermal cycle test is prevented, thereby providing a highly reliable semiconductor device. In a semiconductor device having a structure in which interlayer insulators in which buried wires each having a main electric conductive layer made of copper are formed and cap insulators of the buried wires are stacked, the cap insulator having a relatively high Young's modulus and contacting by its upper surface with the interlayer insulator made of a Low-k film having a relatively low Young's modulus is formed so as not to be provided in an edge portion of the semiconductor device.

Abstract: In a semiconductor device having a Low-k film as an interlayer insulator, peeling of the interlayer insulator in a thermal cycle test is prevented, thereby providing a highly reliable semiconductor device. In a semiconductor device having a structure in which interlayer insulators in which buried wires each having a main electric conductive layer made of copper are formed and cap insulators of the buried wires are stacked, the cap insulator having a relatively high Young's modulus and contacting by its upper surface with the interlayer insulator made of a Low-k film having a relatively low Young's modulus is formed so as not to be provided in an edge portion of the semiconductor device.

Abstract: A metal layer (7), a metallic compound layer (8) and a metal layer (9) are stacked in this order when viewed from the side of a first copper interconnect line (2) and an interlayer insulating film (5) to constitute a second conductive barrier layer (20). As the material for the metal layers (7) and (9), an element having an atomic weight higher than that of copper such as tungsten (W) or tantalum (Ta) is applicable. A second copper interconnect line (6) is conductively connected to the first copper interconnect line (2) at a contact hole (12) through the second conductive barrier layer (20). As the ratio of the volume of the second copper interconnect line (6) at the region for filling a trench (11) to the volume of the second copper interconnect line (6) at the region for filling the contact hole (12) increases, tensile stress to be concentrated at the contact hole (12) becomes greater. As a result, a void is likely to be generated in the contact hole (12).

Abstract: A wire width and a wiring space of each of signal wires 1 and ground/power wires 2 are determined to be a wire width W1 (the minimum wire width) and a wiring space S1, respectively. A wire width and a wiring space of the via-hole neighboring region 1a or 2a are determined to be a wire width W2 (>W1) and a wiring space S2 (<S1), respectively. The wire widths W1 and W2 and the wiring spaces S1 and S2 are respectively determined so as to maintain the minimum wiring pitch P. The wiring space S1 is determined also so as to satisfy {S1/P≧0.6}. Further, the signal wires 1 and the ground/power wires 2 have the same wire thickness of a wire thickness T1 which allows an aspect ratio (T1/W1) to be equal to, or higher than, 2.

Abstract: A metal layer (7), a metallic compound layer (8) and a metal layer (9) are stacked in this order when viewed from the side of a first copper interconnect line (2) and an interlayer insulating film (5) to constitute a second conductive barrier layer (20). As the material for the metal layers (7) and (9), an element having an atomic weight higher than that of copper such as tungsten (W) or tantalum (Ta) is applicable. A second copper interconnect line (6) is conductively connected to the first copper interconnect line (2) at a contact hole (12) through the second conductive barrier layer (20). As the ratio of the volume of the second copper interconnect line (6) at the region for filling a trench (11) to the volume of the second copper interconnect line (6) at the region for filling the contact hole (12) increases, tensile stress to be concentrated at the contact hole (12) becomes greater. As a result, a void is likely to be generated in the contact hole (12).

Abstract: A wire width and a wiring space of each of signal wires 1 and ground/power wires 2 are determined to be a wire width W1 (the minimum wire width) and a wiring space S1, respectively. A wire width and a wiring space of the via-hole neighboring region 1a or 2a are determined to be a wire width W2 (>W1) and a wiring space S2 (<S1), respectively. The wire widths W1 and W2 and the wiring spaces S1 and S2 are respectively determined so as to maintain the minimum wiring pitch P. The wiring space S1 is determined also so as to satisfy {S1/P≧0.6}. Further, the signal wires 1 and the ground/power wires 2 have the same wire thickness of a wire thickness T1 which allows an aspect ratio (T1/W1) to be equal to, or higher than, 2.

Abstract: A metal layer (7), a metallic compound layer (8) and a metal layer (9) are stacked in this order when viewed from the side of a first copper interconnect line (2) and an interlayer insulating film (5) to constitute a second conductive barrier layer (20). As the material for the metal layers (7) and (9), an element having an atomic weight higher than that of copper such as tungsten (W) or tantalum (Ta) is applicable. A second copper interconnect line (6) is conductively connected to the first copper interconnect line (2) at a contact hole (12) through the second conductive barrier layer (20). As the ratio of the volume of the second copper interconnect line (6) at the region for filling a trench (11) to the volume of the second copper interconnect line (6) at the region for filling the contact hole (12) increases, tensile stress to be concentrated at the contact hole (12) becomes greater. As a result, a void is likely to be generated in the contact hole (12).

Abstract: A metal layer (7), a metallic compound layer (8) and a metal layer (9) are stacked in this order when viewed from the side of a first copper interconnect line (2) and an interlayer insulating film (5) to constitute a second conductive barrier layer (20). As the material for the metal layers (7) and (9), an element having an atomic weight higher than that of copper such as tungsten (W) or tantalum (Ta) is applicable. A second copper interconnect line (6) is conductively connected to the first copper interconnect line (2) at a contact hole (12) through the second conductive barrier layer (20). As the ratio of the volume of the second copper interconnect line (6) at the region for filling a trench (11) to the volume of the second copper interconnect line (6) at the region for filling the contact hole (12) increases, tensile stress to be concentrated at the contact hole (12) becomes greater. As a result, a void is likely to be generated in the contact hole (12).

Abstract: Highly refractory titanium silicide structure comprises a titanium silicide film formed on a silicon crystal surface and a thermal oxide film formed on this titanium silicide film. A manufacturing method of the highly refractory titanium silicide is as follows. Initially, titanium is deposited on surfaces including a silicon crystal surface to form a titanium film (12) of a predetermined thickness. This titanium film (12) is then heat-treated in vacuum or in a certain atmosphere which does not cause any oxidation, to form a titanium silicide film (13). Subsequently, further heat treatment at temperatures between 600° C. and 1,000° C. in oxygen atmosphere is done for a predetermined time to oxidize the surface of the titanium silicide film (13). This oxidization of the surface of the titanium silicide film (13) restrains agglomeration in the titanium silicide which might occur in the subsequent annealing, so that the resistance value increase can be prevented.

Abstract: An aluminum interconnection film has a three layered structure of an aluminum alloy film, a tungsten film, and a titanium nitride film. An aluminum interconnection film and a second aluminum interconnection film are electrically connected through a through hole formed in a silicon oxide film. Because light reflectivity of the titanium nitride film is low, the exposed area of the resist can be kept within a predetermined area even if photolithography is carried out above a step where light is irregularly reflected. Therefore, it is possible to form a through hole of a desired dimension even if the through hole is formed above the step. Even if the titanium nitride film is etched and removed in forming the through hole, the aluminum alloy film is not exposed since the etching speed of the silicon oxide film is considerably slower than that of the tungsten film. The problem of denatured layer formation and residue formation caused by exposure of aluminum alloy film does not occur.

Abstract: A method of forming a multi-layer interconnection is provided by which a resist pattern can be precisely formed by maintaining a uniform resist pattern film thickness and such problems as reduced electric resistance of a connecting portion and defective connection between a first interconnection layer and a second interconnection layer will not occur by ensuring a sufficient diameter of a contact hole. The method includes the steps of: removing a portion of an insulating layer having a main surface and covering a first conductive layer to form a hole reaching the first conductive layer in the insulating layer; forming an organic layer at least filling the hole; removing a portion of the insulating layer at a portion at which the insulating layer contacts an organic layer filling the hole; removing the organic layer filling the hole to form a recessed portion continuous to the hole in the insulating layer; and forming a second conductive layer in such a manner that it fills the hole and the recessed portion.

Abstract: A semiconductor device comprising conductors electrically connected through a contact hole interlayer insulation layer with a trilayer barrier layer comprising a titanium silicide layer, titanium silicide layer formed on the titanium silicide by collimation sputtering, and a thermally nitrided titanium formed on the titanium nitride layer. The use of a trilayer barrier layer enables through the capacity of the collimation sputtering apparatus to be increased, prevents particles from occurring, and formation of a low resistance electrical connection between conductors, in addition to preventing diffusion from the titanium nitride layer and the second titanium layer to the thermally nitrided titanium layer, and between conductors.

Abstract: An aluminum interconnection film has a three layered structure of an aluminum alloy film, a tungsten film, and a titanium nitride film. An aluminum interconnection film and an aluminum interconnection film are electrically connected through a through hole formed in a silicon oxide film, one embodiment using a tungsten plug for the electrical connection. Because light reflectivity of the titanium nitride film is low, the exposed area of the resist can be kept within a predetermined area even if photolithography is carried out above a step where light is irregularly reflected. Therefore, it is possible to form a through hole of a desired dimension even if the through hole is formed above the step. Even if the titanium nitride film is etched and removed in forming the through hole, the aluminum alloy film is not exposed since the etching speed of the silicon oxide film is considerably slower than that of the tungsten film.

Abstract: An aluminum interconnection film has a three layered structure of an aluminum alloy film, a tungsten film, and a titanium nitride film. An aluminum interconnection film and an aluminum interconnection film are electrically connected through a through hole formed in a silicon oxide film. Because light reflectivity of the titanium nitride film is low, the exposed area of the resist can be kept within a predetermined area even if photolithography is carried out above a step where light is irregularly reflected. Therefore, it is possible to form a through hole of a desired dimension even if the through hole is formed above the step. Even if the titanium nitride film is etched and removed in forming the through hole, the aluminum alloy film is not exposed since the etching speed of the silicon oxide film is considerably slower than that of the tungsten film. The problem of denatured layer formation and residue formation caused by exposure of aluminum alloy film does not occur.

Abstract: A vertical MOS transistor having its channel length determined by the thickness of an insulating layer provided over a semiconductor substrate, rather than by the depth of a trench in which the transistor is formed. As a result, the characteristics of the transistor as relatively unaffected by doping and heat-treatment steps which are performed during formation. Also, the transistor may be formed so as to occupy very little surface area, making it suitable for application in high-density DRAMs.

Abstract: The present invention relates to a semiconductor device having a contact electrode structure and a method of manufacturing the same. An insulating layer is provided in a second semiconductor layer or in a junction part between the second semiconductor layer and a first semiconductor layer correspondence to a contact hole. Therefore, even if a pit generated at a junction part between the second semiconductor layer and a conductive layer in the contact hole grows, the growth of the pit is inhibited by the insulating layer, whereby leakage current caused between the first and second semiconductor layers can be reduced, a reliability of the device being thus enhanced.

Abstract: A semiconductor memory device includes a first trench serving as a memory cell formed in a p type semiconductor substrate, a first n type semiconductor region formed adjacent to the trench region and on the major surface of the semiconductor substrate, a conductive layer serving as an electron active region formed adjacent to the first n type region and on the major surface of the semiconductor substrate, a second n type semiconductor region formed adjacent to the electron active region and on the major surface of the semiconductor substrate, a second trench formed adjacent to the second n type semiconductor region in the major surface of the semiconductor substrate which is shallower than the first trench, an interconnection layer serving as a bit line formed in a self-aligning manner in the sidewall portion of the second trench which is shallower than the first trench and a gate electrode serving as a word line formed in the upper portion of the conductive layer through an oxide film.

Abstract: The present invention relates to a semiconductor device having a contact electrode structure and a method of manufacturing the same. An insulating layer is provided in a second semiconductor layer or in a junction part between the second semiconductor layer and a first semiconductor layer correspondence to a contact hole. Therefore, even if a pit generated at a junction part between the second semiconductor layer and a conductive layer in the contact hole grows, the growth of the pit is inhibited by the insulating layer, whereby leakage current caused between the first and second semiconductor layers can be reduced, a reliability of the device being thus enhanced.

Abstract: A vertical MOS transistor having its channel length determined by the thickness of an insulating layer provided over a semiconductor substrate, rather than by the depth of a trench in which the transistor is formed. As a result, the characteristics of the transistor as relatively unaffected by doping and heat-treatment steps which are performed during formation. Also, the transistor may be formed so as to occupy very little surface area, making it suitable for application in high-density DRAMs.