Abstract: Enabling and disabling of a plurality of internal buses (77A, 77B) are determined according to mode information recorded in a mode switching circuit (20) in an LSI, and the LSI is provided with external terminals only for data bus connection corresponding to a requested function, thereby a plurality of external data bus connections are realized by using a single hardware.

Abstract: Video data recording using a plurality of video camera devices can be performed more conveniently than in the conventional technique. A video camera device working as a parent device has a signal sending/receiving function and a control function for the whole system, and a video camera device working as a child device has a signal sending/receiving function. The parent device sends synchronization data for time synchronization, and each child device performs a shooting operation in time synchronization with the parent device in accordance with the received synchronization data.

Abstract: An image coding apparatus includes a coding unit 100 for generating a code A, a coding unit 110 for generating a code B, an image reproduction unit 200, an image reproduction memory 204, and a motion vector detection unit 300. The motion vector detection unit 300 detects a motion vector using an image in the image reproduction memory 204, whereby the coding unit 100 generates the code A, while the image reproduction unit 200 reconstructs an image on the basis of output from the coding unit 100 and stores the image in the image reproduction memory 204. In the operation for generating the code B, the coding unit 110 is employed as a coding unit for generating the code B, while commonly employing the image reproduction memory 204, the motion vector detection unit 300, and the image reproduction unit 200 as employed in the generation operation for code A.

Abstract: A motion vector detection device of the present invention includes: a parameter setting section having parameters relating to N (N is a natural number equal to or greater than 2) search regions obtained by dividing at least a portion of an entire search region in a search frame; a motion vector detection section for calculating an evaluation value which indicates a degree of correlation between an encoded object block in an object frame and a candidate block in one of the N search regions and for calculating a motion vector based on the evaluation value; a result storage section for storing the motion vector and the evaluation value calculated by the motion vector detection section; and a control section for controlling the motion vector detection section to calculate motion vectors and evaluation values for M (1≦M≦N) different ones of the N search regions until a predetermined condition is satisfied, for receiving the motion vectors and the evaluation values from the result storage section, and for det

Abstract: An image coding apparatus includes a coding unit 100 for generating a code A, a coding unit 110 for generating a code B, an image reproduction unit 200, an image reproduction memory 204, and a motion vector detection unit 300. The motion vector detection unit 300 detects a motion vector using an image in the image reproduction memory 204, whereby the coding unit 100 generates the code A, while the image reproduction unit 200 reconstructs an image on the basis of output from the coding unit 100 and stores the image in the image reproduction memory 204. In the operation for generating the code B, the coding unit 110 is employed as a coding unit for generating the code B, while commonly employing the image reproduction memory 204, the motion vector detection unit 300, and the image reproduction unit 200 as employed in the generation operation for code A.

Abstract: An n-channel active region, a p-channel active region and an isolation insulating film are formed, and a silicon film is deposited via a gate insulating film. After introducing n-type impurities into the n-channel region and p-type impurities into the p-channel region, a silicon gate electrode is formed in such a manner that its width is enlarged only in the boundary portion between the n-channel region and the p-channel region. After forming a side wall insulating film, an n-channel diffusion layer and a p-channel diffusion layer, a metal silicide layer is formed in a self-aligned manner on the surfaces of the silicon gate electrode, the n-channel diffusion layer and the p-channel diffusion layer.

Abstract: The present invention provides an image coding apparatus and its motion vector detection method, which can reduce a system cost also when the throughput of image data is increased. The image coding apparatus of the present invention comprises a search range frame memory 40 for outputting a search range for motion vector detection, a coding target frame memory 50 for outputting a coding target block, and a motion compensation unit 210 for performing motion compensation by using the coding target block which is input from the coding target frame memory 50 via a second data bus and the search range for the motion vector detection, which is input from the search range frame memory 40 via a first data bus, and obtaining a candidate block having a highest correlation with the coding target block in the search range.

Abstract: Video data recording using a plurality of video camera devices can be performed more conveniently than in the conventional technique. A video camera device working as a parent device has a signal sending/receiving function and a control function for the whole system, and a video camera device working as a child device has a signal sending/receiving function. The parent device sends synchronization data for time synchronization, and each child device performs a shooting operation in time synchronization with the parent device in accordance with the received synchronization data.

Abstract: According to the invention, a motion vector can be accurately and efficiently detected with regard to any type of images having a variety of characteristics. A motion vector detection unit detects a motion vector with regard to a coding target block on the basis of correlation with a candidate block within a search range. A search range storing memory stores pixel data of an original search range, and supplies, to the motion vector detection unit, pixel data of a search range in accordance with a memory address. A control unit sets the size and the position of the search range on the basis of the motion vector and the correlation evaluation value supplied from the motion vector detection unit, and generates pixel widths in the horizontal and vertical directions of the search range and an offset value corresponding to the relative position to the original search range.

Abstract: An operation controller, an operation unit and a memory are provided. The operation controller always receives a non-gated clock signal from a clock controller. When an operation initiating signal and a parameter signal indicating resources to be used in the operation unit are generated by a microcontroller, the operation controller asserts a request signal. In response to the request signal, respective gated clock signals are supplied from the clock controller to the operation unit and to the memory. The operation controller determines whether or not a status signal supplied from the operation unit satisfies a predetermined end condition. If the signal satisfies the end condition, the operation controller negates the request signal. As a result, the supply of the clock signals to the operation unit and to the memory is stopped.

Abstract: In detecting a motion vector, sub-sampling is more selectively and adaptively set in terms of power consumption and detection performance. A correlation calculation section includes a plurality of correlation calculation blocks, each calculating correlation between a block to be coded and an associated candidate block within a search range. Each correlation calculation block is supplied with a different group of pixels of the block to be coded and an associated group of pixels of the associated candidate block, and calculates the correlation between the two groups of pixels supplied. A control section selectively sets sub-sampling in accordance with image feature information such as the frequency components of the block to be coded or operating state information such as the power left in a battery. And, in accordance with the setting of sub-sampling, the control section selectively operates part or all of the correlation calculation blocks of the correlation calculation section.

Abstract: There is provided a correlation degree operation apparatus in which the search area is readily extensible, in which a high-speed process can be assured even though the search area is extended, and which can be formed in a simple arrangement. The search area memory stores the picture element data of a search area including ((m.times.M).times.L) candidate blocks. The correlation degree operation unit executes an operation of a degree of correlation between a reference picture block and each of the candidate blocks, with the use of picture element data supplied from the search area memory, this operation being executed by a pipeline process for each candidate block group composed of (M.times.L) candidate blocks. The search area memory has the function of supplying four picture element data at the same clock cycle. This enables the correlation degree operation unit to continuously execute the pipeline processes for the candidate block groups.

Abstract: An instruction address that is referred to by a microprocessor unit is inputted over an instruction address bus and is stored. While counting the number of times a clock is fed to the microprocessor unit, a comparison is made between the stored instruction address and an instruction address that the microprocessor provides onto the instruction address bus. A clock count value, obtained at the time when the aforesaid instruction addresses agree, is stored. If a stored instruction address and an instruction address on the instruction address bus agree for every stored clock count value, then the microprocessor is judged to repeatedly execute a sequence of instructions and the loop count value is incremented by one. When the loop count value exceeds a predetermined value, the microprocessor is judged to be placed in an idle state and the clock frequency is lowered.

Abstract: A program controlled processor comprises a scalar processing unit 101 for normal data (=scalar) operations and branch processing, a plurality of vector processing units 102 of identical structure, a vector distributor 103 for distributing input data as block vectors to vector memory 304 in each vector processing unit 102, a vector coupler 104 for coupling the block vectors stored in vector memory 404 in each vector processing unit 102 to provide output vectors, an instruction memory 105 for storing the operations of these circuit blocks as an operating program, a sequencer 106 for sequentially reading the instruction memory 105, and a decoder 107 for interpreting the read instructions and outputting a control signal to each circuit block. The scalar processing unit 101 comprises a scalar bus input enabling the scalar processing unit 101 to refer scalar registers in the vector processing units 102.

Abstract: In a program control type processor for executing plural instructions including a vector pipeline instruction including a data processor for executing a pipeline operation, there is provided a program controller including a program memory, a program counter and a decoder, and is further provided an address generator and a data memory. When the vector pipeline instruction is read out from the program memory and is decoded by the decoder, the program controller stops the program counter and outputs a start signal, and thereafter, controls an operation of the data processor according to the contents of the vector pipeline instruction.