Patents by Inventor Akihiko Ohwada
Akihiko Ohwada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11599073Abstract: A problem is inputted into an operation unit. A computation unit searches for a ground state of an Ising model. A management unit converts the problem inputted from the operation unit to the Ising model, inputs the Ising model produced by conversion and initial operating conditions into the computation unit, and has the computation unit search for the ground state using overall operating conditions produced by changing the initial operating conditions based on a result of the computation unit searching for the ground state using the initial operating conditions.Type: GrantFiled: February 25, 2019Date of Patent: March 7, 2023Assignee: FUJITSU LIMITEDInventors: Jumpei Koyama, Kazuya Takemoto, Motomu Takatsu, Satoshi Matsubara, Takayuki Shibasaki, Noboru Yoneoka, Toshiyuki Miyazawa, Akihiko Ohwada, Sanroku Tsukamoto
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Publication number: 20190286077Abstract: A problem is inputted into an operation unit. A computation unit searches for a ground state of an Ising model. A management unit converts the problem inputted from the operation unit to the Ising model, inputs the Ising model produced by conversion and initial operating conditions into the computation unit, and has the computation unit search for the ground state using overall operating conditions produced by changing the initial operating conditions based on a result of the computation unit searching for the ground state using the initial operating conditions.Type: ApplicationFiled: February 25, 2019Publication date: September 19, 2019Applicant: FUJITSU LIMITEDInventors: Jumpei KOYAMA, Kazuya TAKEMOTO, Motomu TAKATSU, Satoshi MATSUBARA, Takayuki SHIBASAKI, Noboru YONEOKA, Toshiyuki MIYAZAWA, Akihiko OHWADA, Sanroku TSUKAMOTO
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Patent number: 9269186Abstract: A computer-readable recording medium stores a visualization program that renders an internal organ and causes a computer to execute a process that includes generating along an input normal vector, a given stereoscopic shape; calculating an overlapping portion that overlaps the given stereoscopic shape and the shape of the internal organ; changing a degree of transparency of the overlapping portion; and rendering the shape of the internal organ to include the overlapping portion for which the degree of transparency has been changed.Type: GrantFiled: June 28, 2013Date of Patent: February 23, 2016Assignees: FUJITSU LIMITED, THE UNIVERSITY OF TOKYOInventors: Masahiro Watanabe, Satoshi Fuchikami, Akihiko Ohwada, Yoshimasa Kadooka, Toshiaki Hisada, Seiryo Sugiura, Takumi Washio, Jun-ichi Okada
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Publication number: 20140002450Abstract: A computer-readable recording medium stores a visualization program that renders an internal organ and causes a computer to execute a process that includes generating along an input normal vector, a given stereoscopic shape; calculating an overlapping portion that overlaps the given stereoscopic shape and the shape of the internal organ; changing a degree of transparency of the overlapping portion; and rendering the shape of the internal organ to include the overlapping portion for which the degree of transparency has been changed.Type: ApplicationFiled: June 28, 2013Publication date: January 2, 2014Applicants: The University of Tokyo, FUJITSU LIMITEDInventors: Masahiro WATANABE, Satoshi FUCHIKAMI, Akihiko OHWADA, Yoshimasa KADOOKA, Toshiaki HISADA, Seiryo SUGIURA, Takumi WASHIO, Jun-ichi OKADA
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Patent number: 7676669Abstract: The load/sense control of the setting value that corresponds to the processor core for CMP, etc. processors that have multi-cores realize, for such processors with multi-core structures, the shortening of system boot time during multi-core operation, flexible debugging methods, and improvement of yield with the aid of partial core quality product chips at time of semiconductor production, by equipping a core selection flag register that maintains the status of each core, and controlling the output to the core block from the processor common block through that core selection flag register status.Type: GrantFiled: October 25, 2007Date of Patent: March 9, 2010Assignee: Fujitsu LimitedInventor: Akihiko Ohwada
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Patent number: 7353440Abstract: In processors having multiple cores, such as CMPs, an independent MISR test pattern compression circuit is provided for each logic block, which makes it possible to perform LSI tests more efficiently. A processor includes a plurality of logic block circuits, which include at least a first processor core circuit and a second processor core circuit, each processor core circuit having a scan chain circuit and being operable independently, and a common block circuit having a scan chain circuit and a cache circuit that is shared by the first processor core circuits and the second processor core circuits. The processor further includes, for each logic block, a test pattern generating circuit operable to generate a test pattern and input the test pattern to the scan chain of each logic block circuit, and a test pattern compression circuit operable to accept as input and compress the test pattern output by the scan chain of each logic block circuit.Type: GrantFiled: October 19, 2004Date of Patent: April 1, 2008Assignee: Fujitsu LimitedInventors: Akihiko Ohwada, Tatsumi Nakada, Hitoshi Yamanaka
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Publication number: 20080065867Abstract: The load/sense control of the setting value that corresponds to the processor core for CMP, etc. processors that have multi-cores realize, for such processors with multi-core structures, the shortening of system boot time during multi-core operation, flexible debugging methods, and improvement of yield with the aid of partial core quality product chips at time of semiconductor production, by equipping a core selection flag register that maintains the status of each core, and controlling the output to the core block from the processor common block through that core selection flag register status.Type: ApplicationFiled: October 25, 2007Publication date: March 13, 2008Inventor: Akihiko Ohwada
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Patent number: 7117344Abstract: A processor execution pipeline that includes, a stage latch circuit and a stage latch circuit provided at an input stage of a first processing stage for holding a first processing data SOURCE1 and a second processing data, respectively; an operator provided at the first processing stage for executing a processing by using the first processing data SOURCE1 and the second processing data; a stage latch circuit provided between the first processing stage and a second processing stage for holding an output value of the operator; an operator provided at the second processing stage for executing the processing by using a value of the stage latch circuit when an instruction has been decoded; and an instruction decoder that decodes the instruction to the operator as a through instruction to pass the value of the stage latch circuit through this operator.Type: GrantFiled: June 5, 2000Date of Patent: October 3, 2006Assignee: Fujitsu LimitedInventor: Akihiko Ohwada
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Publication number: 20050289286Abstract: The load/sense control of the setting value that corresponds to the processor core for CMP, etc. processors that have multi-cores realize, for such processors with multi-core structures, the shortening of system boot time during multi-core operation, flexible debugging methods, and improvement of yield with the aid of partial core quality product chips at time of semiconductor production, by equipping a core selection flag register that maintains the status of each core, and controlling the output to the core block from the processor common block through that core selection flag register status.Type: ApplicationFiled: December 16, 2004Publication date: December 29, 2005Inventor: Akihiko Ohwada
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Publication number: 20050240850Abstract: In processors having a multicore, such as CMPs, an independent MISR test pattern compression circuit is provided for each logic block in a multicore processor such as a CMP comprising a plurality of processor cores makes it possible to perform LSI tests more efficiently.Type: ApplicationFiled: October 19, 2004Publication date: October 27, 2005Inventors: Akihiko Ohwada, Tatsumi Nakada, Hitoshi Yamanaka
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Patent number: 6721905Abstract: The present invention provides a processor including a self-diagnostic function. The processor comprises: an arithmetic circuit including an adder-subtracter, which is a diagnostic object; a data storing unit which stores a self-diagnostic data; and a self-diagnostic processing unit. The self-diagnostic processing unit inputs the self-diagnostic data, and then, carries out diagnostic processing so that every bit of the operation result becomes all zero “0” (or all “1”) by the arithmetic circuit.Type: GrantFiled: March 23, 2001Date of Patent: April 13, 2004Assignee: Fujitsu LimitedInventor: Akihiko Ohwada
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Patent number: 6711641Abstract: The operation processing apparatus comprises a trap selecting register which stores trap maps for selecting one operating system in which the operation processing apparatus is applied out of a plurality of operating systems, a read/write controller which selects data for selecting the operating system from the trap selecting register, and a trap type encoder which encodes a trap request from an execution unit such as an integer unit, into trap type code, according to the trap maps corresponding to the selection data.Type: GrantFiled: December 6, 2000Date of Patent: March 23, 2004Assignee: Fujitsu LimitedInventor: Akihiko Ohwada
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Publication number: 20020062462Abstract: The present invention provides a processor including a self-diagnostic function. The processor comprises: an arithmetic circuit including an adder-subtracter, which is a diagnostic object; a data storing unit which stores a self-diagnostic data; and a self-diagnostic processing unit. The self-diagnostic processing unit inputs the self-diagnostic data, and then, carries out diagnostic processing so that every bit of the operation result becomes all zero “0” (or all “1”) by the arithmetic circuit.Type: ApplicationFiled: March 23, 2001Publication date: May 23, 2002Applicant: FUJITSU LIMITEDInventor: Akihiko Ohwada
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Publication number: 20010049762Abstract: The operation processing apparatus comprises a trap selecting register which stores trap maps for selecting one operating system in which the operation processing apparatus is applied out of a plurality of operating systems, a read/write controller which selects data for selecting the operating system from the trap selecting register, and a trap type encoder which encodes a trap request from an execution unit such as an integer unit, into trap type code, according to the trap maps corresponding to the selection data.Type: ApplicationFiled: December 6, 2000Publication date: December 6, 2001Inventor: Akihiko Ohwada