Patents by Inventor Akihiko Tashiro
Akihiko Tashiro has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8161608Abstract: To provide a method of manufacturing a quartz-crystal resonator, in which without adding new processes, a desired quartz-crystal piece can be obtained from a quartz-crystal wafer by etching and electrodes can be provided without restraint. When a quartz-crystal piece 10 is formed, etching masks 6 having dummy regions 44, 48 that are provided at two positions corresponding to corner portions on a +X side of the quartz-crystal piece 10 and extend toward a +X axis direction of a wafer W are formed, and when the quartz-crystal piece 10 is formed, etching in groove portions 7 at positions corresponding to the dummy regions 44, 48 is delayed. Accordingly, it is possible to form the quartz-crystal piece 10 without chipped portions at the corner portions in a state where the quartz-crystal piece 10 and the wafer W are connected to and supported by a connection support portion 11.Type: GrantFiled: December 28, 2009Date of Patent: April 24, 2012Assignee: Nihon Dempa Kogyo Co., Ltd.Inventors: Akihiko Tashiro, Hiroyuki Sasaki
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Publication number: 20100192340Abstract: To provide a method of manufacturing a quartz-crystal resonator, in which without adding new processes, a desired quartz-crystal piece can be obtained from a quartz-crystal wafer by etching and electrodes can be provided without restraint. When a quartz-crystal piece 10 is formed, etching masks 6 having dummy regions 44, 48 that are provided at two positions corresponding to corner portions on a +X side of the quartz-crystal piece 10 and extend toward a +X axis direction of a wafer W are formed, and when the quartz-crystal piece 10 is formed, etching in groove portions 7 at positions corresponding to the dummy regions 44, 48 is delayed. Accordingly, it is possible to form the quartz-crystal piece 10 without chipped portions at the corner portions in a state where the quartz-crystal piece 10 and the wafer W are connected to and supported by a connection support portion 11.Type: ApplicationFiled: December 28, 2009Publication date: August 5, 2010Applicant: Nihon Dempa Kogyo Co., Ltd.Inventors: Akihiko Tashiro, Hiroyuki Sasaki
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Publication number: 20100105154Abstract: A substrate processing method can securely form a metal film by electroless plating on an exposed surface of a base metal, such as interconnects, with increased throughput and without the formation of voids in the base metal. The substrate processing method includes: cleaning a surface of a substrate having a base metal formed in the surface with a cleaning solution comprising an aqueous solution of a carboxyl group-containing organic acid or its salt and a surfactant as an additive; bringing the surface of the substrate after the cleaning into contact with a processing solution comprising a mixture of the cleaning solution and a solution containing a catalyst metal ion, thereby applying the catalyst to the surface of the substrate; and forming a metal film by electroless plating on the catalyst-applied surface of the substrate.Type: ApplicationFiled: January 12, 2010Publication date: April 29, 2010Inventors: XINMING WANG, Daisuke Takagi, Akihiko Tashiro, Yukio Fukunaga, Akira Fukunaga, Akira Owatari, Yukiko Nishioka
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Publication number: 20100075498Abstract: A semiconductor device has interconnects protected with an alloy film having a minimum thickness necessary for producing the effect of preventing diffusion of oxygen, copper, etc., formed more uniformly over an entire surface of a substrate with less dependency to the interconnect pattern of the substrate. The semiconductor device includes, embedded interconnects, formed by filling an interconnect material into interconnect recesses formed in an electric insulator on a substrate, and an alloy film, containing 1 to 9 atomic % of tungsten or molybdenum and 3 to 12 atomic % of phosphorus or boron, formed by electroless plating on at least part of the embedded interconnects.Type: ApplicationFiled: December 2, 2009Publication date: March 25, 2010Inventors: Daisuke TAKAGI, Xinming Wang, Akira Owatari, Akira Fukunaga, Akihiko Tashiro
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Patent number: 7498261Abstract: A metal film-forming method of the present invention can form a metal film having different film qualities in the thickness direction, in a continuous manner using a single processing solution. The metal film-forming method including: providing a substrate having embedded interconnects formed in interconnect recesses provided in a surface of the substrate; and forming a metal film, having different film qualities in the thickness direction, on surfaces of the interconnects in a continuous manner by changing the flow state of a processing solution relative to the surface of the substrate while keeping the surface of the substrate in contact with the processing solution.Type: GrantFiled: September 7, 2005Date of Patent: March 3, 2009Assignee: Ebara CorporationInventors: Xinming Wang, Daisuke Takagi, Akihiko Tashiro, Yukio Fukunaga, Akira Fukunaga, Akira Owatari
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Publication number: 20090000549Abstract: There is provided a substrate processing method and apparatus which can measure and monitor thickness and/or properties of a film formed on a substrate as needed, and quickly correct a deviation in process conditions, and which can therefore stably provide a product of constant quality. A substrate processing method for processing a substrate having a metal and an insulating material exposed on its surface in such a manner that a film thickness of the metal, with an exposed surface of the metal as a reference plane, is selectively or preferentially changed, including measuring a change in the film thickness and/or a film property of the metal during and/or immediately after processing, and monitoring processing and adjusting processing conditions based on results of this measurement.Type: ApplicationFiled: June 30, 2008Publication date: January 1, 2009Inventors: Xinming Wang, Daisuke Takagi, Akihiko Tashiro, Akira Fukunaga
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Patent number: 7407821Abstract: There is provided a substrate processing method and apparatus which can measure and monitor thickness and/or properties of a film formed on a substrate as needed, and quickly correct a deviation in process conditions, and which can therefore stably provide a product of constant quality. A substrate processing method for processing a substrate having a metal and an insulating material exposed on its surface in such a manner that a film thickness of the metal, with an exposed surface of the metal as a reference plane, is selectively or preferentially changed, including measuring a change in the film thickness and/or a film property of the metal during and/or immediately after processing, and monitoring processing and adjusting processing conditions based on results of this measurement.Type: GrantFiled: June 24, 2004Date of Patent: August 5, 2008Assignee: Ebara CorporationInventors: Xinming Wang, Daisuke Takagi, Akihiko Tashiro, Akira Fukunaga
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Patent number: 7374584Abstract: The present invention provides an interconnects-forming method and an interconnects-forming apparatus which can minimize the lowering of processing accuracy in etching, minimize light exposure processing for the formation of interconnect recesses in the production of multi-level interconnects, improve the electromigration resistance of interconnects without impairing the electrical properties of the interconnects, and enhance the reliability of the device.Type: GrantFiled: April 6, 2007Date of Patent: May 20, 2008Assignee: Ebara CorporationInventors: Xinming Wang, Daisuke Takagi, Akihiko Tashiro, Yukio Fukunaga, Akira Fukunaga
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Publication number: 20080067679Abstract: A semiconductor device has interconnects protected with an alloy film having a minimum thickness necessary for producing the effect of preventing diffusion of oxygen, copper, etc., formed more uniformly over an entire surface of a substrate with less dependency to the interconnect pattern of the substrate. The semiconductor device includes, embedded interconnects, formed by filling an interconnect material into interconnect recesses formed in an electric insulator on a substrate, and an alloy film, containing 1 to 9 atomic % of tungsten or molybdenum and 3 to 12 atomic % of phosphorus or boron, formed by electroless plating on at least part of the embedded interconnects.Type: ApplicationFiled: September 22, 2005Publication date: March 20, 2008Inventors: Daisuke Takagi, Xinming Wang, Akira Owatari, Akira Fukunaga, Akihiko Tashiro
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Publication number: 20080000776Abstract: A substrate processing method can securely form a metal film by electroless plating on an exposed surface of a base metal, such as interconnects, with increased throughput and without the formation of voids in the base metal. The substrate processing method includes: cleaning a surface of a substrate having a base metal formed in the surface with a cleaning solution comprising an aqueous solution of a carboxyl group-containing organic acid or its salt and a surfactant as an additive; bringing the surface of the substrate after the cleaning into contact with a processing solution comprising a mixture of the cleaning solution and a solution containing a catalyst metal ion, thereby applying the catalyst to the surface of the substrate; and forming a metal film by electroless plating on the catalyst-applied surface of the substrate.Type: ApplicationFiled: August 29, 2007Publication date: January 3, 2008Inventors: Xinming Wang, Daisuke Takagi, Akihiko Tashiro, Yukio Fukunaga, Akira Fukunaga, Akira Owatari, Yukiko Nishioka
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Patent number: 7285492Abstract: A substrate processing method can securely form a metal film by electroless plating on an exposed surface of a base metal, such as interconnects, with increased throughput and without the formation of voids in the base metal. The substrate processing method includes: cleaning a surface of a substrate having a base metal formed in the surface with a cleaning solution comprising an aqueous solution of a carboxyl group-containing organic acid or its salt and a surfactant as an additive; bringing the surface of the substrate after the cleaning into contact with a processing solution comprising a mixture of the cleaning solution and a solution containing a catalyst metal ion, thereby applying the catalyst to the surface of the substrate; and forming a metal film by electroless plating on the catalyst-applied surface of the substrate.Type: GrantFiled: January 24, 2005Date of Patent: October 23, 2007Assignee: Ebara CorporationInventors: Xinming Wang, Daisuke Takagi, Akihiko Tashiro, Yukio Fukunaga, Akira Fukunaga, Akira Owatari, Yukiko Nishioka, Tsuyoshi Sahoda
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Publication number: 20070228569Abstract: The present invention provides an interconnects-forming method and an interconnects-forming apparatus which can minimize the lowering of processing accuracy in etching, minimize light exposure processing for the formation of interconnect recesses in the production of multi-level interconnects, improve the electromigration resistance of interconnects without impairing the electrical properties of the interconnects, and enhance the reliability of the device.Type: ApplicationFiled: April 6, 2007Publication date: October 4, 2007Inventors: Xinming Wang, Daisuke Takagi, Akihiko Tashiro, Yukio Fukunaga, Akira Fukunaga
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Patent number: 7217653Abstract: The present invention provides an interconnects-forming method and an interconnects-forming apparatus which can minimize the lowering of processing accuracy in etching, minimize light exposure processing for the formation of interconnect recesses in the production of multi-level interconnects, improve the electromigration resistance of interconnects without impairing the electrical properties of the interconnects, and enhance the reliability of the device.Type: GrantFiled: July 22, 2004Date of Patent: May 15, 2007Assignee: Ebara CorporationInventors: Xinming Wang, Daisuke Takagi, Akihiko Tashiro, Yukio Fukunaga, Akira Fukunaga
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Publication number: 20060057839Abstract: A metal film-forming method of the present invention can form a metal film having different film qualities in the thickness direction, in a continuous manner using a single processing solution. The metal film-forming method including: providing a substrate having embedded interconnects formed in interconnect recesses provided in a surface of the substrate; and forming a metal film, having different film qualities in the thickness direction, on surfaces of the interconnects in a continuous manner by changing the flow state of a processing solution relative to the surface of the substrate while keeping the surface of the substrate in contact with the processing solution.Type: ApplicationFiled: September 7, 2005Publication date: March 16, 2006Inventors: Xinming Wang, Daisuke Takagi, Akihiko Tashiro, Yukio Fukunaga, Akira Fukunaga, Akira Owatari
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Publication number: 20050245080Abstract: A substrate processing method can securely form a metal film by electroless plating on an exposed surface of a base metal, such as interconnects, with increased throughput and without the formation of voids in the base metal. The substrate processing method includes: cleaning a surface of a substrate having a base metal formed in the surface with a cleaning solution comprising an aqueous solution of a carboxyl group-containing organic acid or its salt and a surfactant as an additive; bringing the surface of the substrate after the cleaning into contact with a processing solution comprising a mixture of the cleaning solution and a solution containing a catalyst metal ion, thereby applying the catalyst to the surface of the substrate; and forming a metal film by electroless plating on the catalyst-applied surface of the substrate.Type: ApplicationFiled: January 24, 2005Publication date: November 3, 2005Inventors: Xinming Wang, Daisuke Takagi, Akihiko Tashiro, Yukio Fukunaga, Akira Fukunaga, Akira Owatari, Yukiko Nishioka, Tsuyoshi Sahoda
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Publication number: 20050064702Abstract: The present invention provides an interconnects-forming method and an interconnects-forming apparatus which can minimize the lowering of processing accuracy in etching, light exposure or the like processing for the formation of interconnect recesses in the production of multi-level interconnects, can improve the electromigration resistance of interconnects without impairing the electrical properties of the interconnects, and can enhance the reliabilityof the device.Type: ApplicationFiled: July 22, 2004Publication date: March 24, 2005Inventors: Xinming Wang, Daisuke Takagi, Akihiko Tashiro, Yukio Fukunaga, Akira Fukunaga
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Publication number: 20050022909Abstract: There is provided a substrate processing method which is capable of lowering the initial cost and the running cost of an apparatus, does not require a wide installation space, does not degrade electrical characteristics such as an interconnect resistance and a leakage current, and is capable of efficiently forming a high-quality alloy film on the surface of a metal region. The substrate processing method including; preparing a substrate having a metal region on a surface thereof, performing a pre-plating treatment by bringing a pretreatment liquid into contact with the surface of the substrate to modify the entire surface thereof, removing the pretreatment liquid remaining on the surface of the substrate in a rinsing treatment, performing an electroless plating process on the surface of the substrate to selectively form an alloy film on the surface of the metal region, and post-cleaning the substrate after the electroless plating process and drying the substrate.Type: ApplicationFiled: March 19, 2004Publication date: February 3, 2005Inventors: Xinming Wang, Daisuke Takagi, Akihiko Tashiro, Akira Fukunaga, Akira Owatari
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Publication number: 20050009340Abstract: A capping film serving as an interconnect protective film formed on a surface of interconnect metal on a semiconductor substrate is formed after forming a catalyst layer for electroless plating under low oxygen concentration condition. A method for forming a capping film for protecting a surface of interconnect metal includes preparing a metal catalyst solution containing a metal element nobler than interconnect metal and having dissolved oxygen concentration of 7 ppm or less, bringing said metal catalyst solution into contact with a surface of interconnect metal to form a metal catalyst layer on the surface of the interconnect metal, and performing electroless plating to form a capping film on the surface of the interconnect metal.Type: ApplicationFiled: July 7, 2004Publication date: January 13, 2005Inventors: Yasuhiko Saijo, Masashi Shimoyama, Hiroshi Yokota, Akihiko Tashiro, Xinming Wang, Daisuke Takagi
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Publication number: 20050009213Abstract: There is provided a substrate processing method and apparatus which can measure and monitor the thickness and/or properties of a film formed on a substrate as needed, and quickly correct a deviation in the process conditions, and which can therefore stably provide a product of constant quality. A substrate processing method for processing a substrate with a metal and an insulating material exposed on its surface in such a manner that the film thickness of the metal portion with the exposed surface of the metal as a reference plane is selectively or preferentially changed, including measuring a change in the film thickness and/or a film property of the metal portion during and/or immediately after processing, and monitoring the processing and adjusting the processing conditions based on the results of measurement.Type: ApplicationFiled: June 24, 2004Publication date: January 13, 2005Inventors: Xinming Wang, Daisuke Takagi, Akihiko Tashiro, Akira Fukunaga
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Patent number: 6024563Abstract: A device which allows easy observation of discrepancies between the upper and lower jaw comprises an upper bow (100) and a lower bow (200) which separately hold in place an upper jaw model (UM) and a lower jaw model (LM) prepared based on impressions and position these upper and lower jaw models (UM) and (LM) opposite to each other, checker pins (310) in the upper bow (200) which are positioned at a location corresponding to the opening/closing axis of the upper jaw model (UM) and lower jaw model (LM) and along the opening/closing axis, and checker plates (300) in the upper bow (100) positioned in such a manner that their outer surfaces (306) are perpendicular to the opening/closing axis and adjacent to the tips of the checker pins (310).Type: GrantFiled: July 10, 1997Date of Patent: February 15, 2000Assignee: Sankin Kogyo Kabushiki KaishaInventors: Kazuo Shiraishi, Akihiko Tashiro, Tadashi Kimura