Abstract: A plug connector includes: a jack portion into which a pin of a microphone-equipped headphone plug in which a speaker contact portion connected to a speaker of a headphone, a ground contact portion connected to a ground wire of the headphone, and a microphone contact portion connected to a microphone of the headphone are sequentially formed in an axial direction, the jack portion having a first contact which is in contact with the speaker contact portion, a second contact which is in contact with the ground contact portion, and a third contact which is in contact with the microphone contact portion; a bias circuit configured to supply a bias voltage to the third contact through a resistor; and a control circuit configured to detect that the pin is extracted from the jack portion, based on a change of a potential of the third contact.

Abstract: A test signal supplying device includes a first external terminal, a second external terminal being applied with a predetermined electric potential, an internal load, a first terminal that is connected to the first external terminal through the internal load, a second terminal that is connected to the first external terminal without passing through the internal load, a test signal generating section that generates a test signal and supplies the test signal to the second terminal, a detecting section that detects an amplitude of the test signal, and a controlling section that measures an impedance of an external load connected to the first and second external terminals based on the detected amplitude of the test signal.

Abstract: The biological optical measurement instrument is provided with a mobile position sensor that can move in a 3-dimensional space and that detects spatial position in the 3-dimensional space, a head-surface image creating unit that creates a head-surface image of an object and a head-surface point creating unit that creates, on the head-surface image, a head-surface point corresponding to the spatial position of the mobile position sensor.

Abstract: A plug connector includes: a jack portion into which a pin of a microphone-equipped headphone plug in which a speaker contact portion connected to a speaker of a headphone, a ground contact portion connected to a ground wire of the headphone, and a microphone contact portion connected to a microphone of the headphone are sequentially formed in an axial direction, the jack portion having a first contact which is in contact with the speaker contact portion, a second contact which is in contact with the ground contact portion, and a third contact which is in contact with the microphone contact portion; a bias circuit configured to supply a bias voltage to the third contact through a resistor; and a control circuit configured to detect that the pin is extracted from the jack portion, based on a change of a potential of the third contact.

Abstract: A test signal supplying device includes a first external terminal, a second external terminal being applied with a predetermined electric potential, an internal load, a first terminal that is connected to the first external terminal through the internal load, a second terminal that is connected to the first external terminal without passing through the internal load, a test signal generating section that generates a test signal and supplies the test signal to the second terminal, a detecting section that detects an amplitude of the test signal, and a controlling section that measures an impedance of an external load connected to the first and second external terminals based on the detected amplitude of the test signal.

Abstract: A D/A converter formed on a semiconductor substrate includes a plurality of resistance strings which are provided between a low voltage terminal and a high voltage terminal, each of the resistance strings including a plurality of resistances connected in series. The resistance strings to be connected at odd-numbered positions are arranged on the substrate in order of increasing in a direction from a near side of the terminal to which the low voltage is applied to the far side thereof, and the resistance strings to be connected at even-numbered positions are arranged on the substrate in order of increasing in a direction from the far side of the terminal to the near side. A voltage at a junction point of the resistances constituting the resistance string is selectively output in accordance with input data to be converted.

Abstract: A phenylenediamine derivative represented by following formula (I) or (II): wherein R1 and R2 each represents a hydrogen atom, a lower alkyl group, or a lower alkoxy group; R3 represents a hydrogen atom or a methyl group; R4 represents a methyl group or an ethyl group; and n and m each is 1, 2, or 3; wherein R1 and R2 each represents a hydrogen atom, a lower alkyl group, a lower alkoxy group, or a cyano group; and n and m each is 1, 2, or 3, is disclosed. These phenylenediamine derivatives are effectively used as antioxidants for rubbers, which scarcely cause vanishing by evaporation or a thermal denaturation even under a high-temperature condition of 150° C. or higher.

Abstract: A D/A converter formed on a semiconductor substrate includes a plurality of resistance strings which are provided between a low voltage terminal and a high voltage terminal, each of the resistance strings including a plurality of resistances connected in series. The resistance strings to be connected at odd-numbered positions are arranged on the substrate in order of increasing in a direction from a near side of the terminal to which the low voltage is applied to the far side thereof, and the resistance strings to be connected at even-numbered positions are arranged on the substrate in order of increasing in a direction from the far side of the terminal to the near side. A voltage at a junction point of the resistances constituting the resistance string is selectively output in accordance with input data to be converted.

Abstract: A signal level shift circuit is provided for different circuit systems operating based on different supply voltages (VDDL, VDDH), wherein a supply voltage detection circuit detects a reduction of a first supply voltage (VDDL) regarding an input signal (IN). A level shift circuit comprises a load circuit portion consisting of PMOS transistors and a drive circuit portion consisting of NMOS transistors, all of which are connected together to form current paths. A switch circuit arranged for the current paths opens when a reduction is detected in the first supply voltage so that both the NMOS transistors are turned on. Thus, it is possible to effectively avoid occurrence of through currents flowing in the level shift circuit. The level shift circuit is followed by a flip-flop, which provides an output signal (OUT) in conformity with a second supply voltage (VDDH).

Abstract: There is provided a D/A converter that is free from a variation in the voltage width of 1 LSB between more significant bits and less significant bits of data for conversion due to variations in characteristics of resistors, transistors, etc. to thereby ensure a higher conversion accuracy than the conventional D/A converter. The eight more significant bits of 12-bit data for conversion are applied to a decoder 21, while the four less significant bits of the same are applied to a current addition circuit 22. The decoder 21 selects one of FET's F0 to F255 based on the eight more significant bits to cause one of voltages divided by a series circuit formed by resistors r0 to r255 to be applied to an operational amplifier 40. On the other hand, switches 30 to 33 of the current addition circuit 22 are switched, respectively, by the four less significant bits to turn respective FET's 35 to 38 on and off.

Abstract: Level shift circuit includes an operational amplifier, and an input resistor having one end connected to an output terminal of an amplifier circuit and the other end connected to the inverted input terminal of the operational amplifier. The level shift circuit further includes a level-shifting resistor of a resistance value R0 having one end connected to the inverted input terminal of the operational amplifier and the other end connected to a ground, and a feedback resistor of a resistance value R1. Reference voltage Vref is applied to the noninverted input terminal of the operational amplifier. Output signal of the level shift circuit represents the output of the amplifier circuit having been shifted in level by a predetermined amount.

Abstract: A signal level shift circuit is provided for different circuit systems operating based on different supply voltages (VDDL, VDDH), wherein a supply voltage detection circuit detects a reduction of a first supply voltage (VDDL) regarding an input signal (IN). A level shift circuit comprises a load circuit portion consisting of PMOS transistors and a drive circuit portion consisting of NMOS transistors, all of which are connected together to form current paths. A switch circuit arranged for the current paths opens when a reduction is detected in the first supply voltage so that both the NMOS transistors are turned on. Thus, it is possible to effectively avoid occurrence of through currents flowing in the level shift circuit. The level shift circuit is followed by a flip-flop, which provides an output signal (OUT) in conformity with a second supply voltage (VDDH).

Abstract: A digital-to-analog-converter is provided which allows a use to set the reference voltage as desired and therefore has improved flexibility. A more significant bit data conversion section converts more significant bit data of digital data into a more significant analog signal corresponding to the more significant bit data by using a reference voltage inputted from outside. A less significant bit data conversion section converts less significant bit data of the digital data into a less significant analog signal corresponding to the less significant bit data. A controller controls the less significant bit data conversion section in such a manner as to output the less significant analog signal according to the reference voltage. An adder adds the more significant analog signal and the less significant analog signal, thereby outputting an analog signal corresponding to the digital data.

Abstract: Level shift circuit includes an operational amplifier, and an input resistor having one end connected to an output terminal of an amplifier circuit and the other end connected to the inverted input terminal of the operational amplifier. The level shift circuit further includes a level-shifting resistor of a resistance value RO having one end connected to the inverted input terminal of the operational amplifier and the other end connected to a ground, and a feedback resistor of a resistance value R1. Reference voltage Vref is applied to the noninverted input terminal of the operational amplifier. Output signal of the level shift circuit represents the output of the amplifier circuit having been shifted in level by a predetermined amount.

Abstract: A phenylenediamine derivative represented by following formula (I) or (II): 1

Abstract: A phenylenediamine derivative represented by following formula (I) or (II): wherein R1 and R2 each represents a hydrogen atom, a lower alkyl group, or a lower alkoxy group; R3 represents a hydrogen atom or a methyl group; R4 represents a methyl group or an ethyl group; and n and m each is 1, 2, or 3; wherein R1 and R2 each represents a hydrogen atom, a lower alkyl group, a lower alkoxy group, or a cyano group; and n and m each is 1, 2, or 3, is disclosed. These phenylenediamine derivatives are effectively used as antioxidants for rubbers, which scarcely cause vanishing by evaporation or a thermal denaturation even under a high-temperature condition of 150° C. or higher.

Abstract: A digital-to-analog-converter is provided which allows a use to set the reference voltage as desired and therefore has improved flexibility. A more significant bit data conversion section converts more significant bit data of digital data into a more significant analog signal corresponding to the more significant bit data by using a reference voltage inputted from outside. A less significant bit data conversion section converts less significant bit data of the digital data into a less significant analog signal corresponding to the less significant bit data. A controller controls the less significant bit data conversion section in such a manner as to output the less significant analog signal according to the reference voltage. An adder adds the more significant analog signal and the less significant analog signal, thereby outputting an analog signal corresponding to the digital data.

Abstract: A phenylenediamine derivative represented by following formula (I) or (II): ##STR1## wherein R.sub.1 and R.sub.2 each represents a hydrogen atom, a lower alkyl group, or a lower alkoxy group; R.sub.3 represents a hydrogen atom or a methyl group; R.sub.4 represents a methyl group or an ethyl group; and n and m each is 1, 2, or 3; ##STR2## wherein R.sub.1 and R.sub.2 each represents a hydrogen atom, a lower alkyl group, a lower alkoxy group, or a cyano group; and n and m each is 1, 2, or 3, is disclosed.These phenylenediamine derivatives are effectively used as antioxidants for rubbers, which scarcely cause vanishing by evaporation or a thermal denaturation even under a high-temperature condition of 150.degree. C. or higher.

Abstract: An information-discriminating circuit has a biasing device that superposes bias voltage on an input signal, and a comparator that discriminates information by comparing an output signal from the biasing device with a threshold value. The difference between the bias voltage and the threshold value is continuously adjusted such that a noise margin is varied according to the amplitude of the input signal.

Abstract: A digital-to-analog (D/A) converter provides superior linearity and reduces glitches by setting optimum dimensions for MOS transistors. The D/A converter is configured from a R-2R ladder circuit and a switching circuit. The R-2R ladder circuit consists of series resistors (R) and shunt resistors (2R), which are connected together at respective nodes corresponding to the bit stages. The switching circuit is configured from MOS transistors which are connected between reference potentials and the shunt resistors for each bit stage. The width/length (W/L) ratios of the MOS transistors are set such that the on-resistances of the transistors are sequentially increased by a factor of 2 in bit-stage descending order from the most significant bit (MSB) to the least significant bit (LSB) to maintain the linearity of the R-2R ladder circuit.