Abstract: In a multiprocessor, one of two local memories can be accessed at a high speed by one of the two processors and also accessed by the other processor. In a multiprocessor, first and second local memories are coupled to first and second processors via first and second local buses. First and second bus bridges are coupled to a system bus and the first and second local buses. First and second bus interface units are coupled to the system bus and the first and second local memories. A high-speed access is made from the first processor to the first local memory via the first local bus. The first local memory is also accessed from the first processor via the first local bus, the first bus bridge, the system bus, and the first and third ports of the second bus interface unit and from the second processor via the second local bus, the second bus bridge, the system bus, and the second and third ports of the first bus interface unit.

Abstract: To allow to use arithmetic circuits of sharable resources by priority with a simple procedure. In a data processing system including central processing units and a plurality of arithmetic circuits, wherein the central processing units are able to supply a command to one arithmetic circuit based on one fetched instruction and supply a command to other arithmetic circuit based on other fetched instruction, a memory circuit is provided which is used to store first information indicating which arithmetic circuit is executing a command, and second information indicating which central processing unit has reserved the arithmetic circuit for execution of the next command. When the arithmetic circuit is already executing a command, reservation of the arithmetic circuit for execution of the next command using the second information of the memory circuit, makes it possible, after the execution, to assign operation commands fast to the arithmetic circuits and cause them to execute the commands.

Abstract: In a multiprocessor, one of two local memories can be accessed at a high speed by one of the two processors and also accessed by the other processor. In a multiprocessor, first and second local memories are coupled to first and second processors via first and second local buses. First and second bus bridges are coupled to a system bus and the first and second local buses. First and second bus interface units are coupled to the system bus and the first and second local memories. A high-speed access is made from the first processor to the first local memory via the first local bus. The first local memory is also accessed from the first processor via the first local bus, the first bus bridge, the system bus, and the first and third ports of the second bus interface unit and from the second processor via the second local bus, the second bus bridge, the system bus, and the second and third ports of the first bus interface unit.