Patents by Inventor Akihiko Tsuzumitani
Akihiko Tsuzumitani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8242567Abstract: In order that a top surface of a gate electrode does not have sharp portions, ends of the top surface of the gate electrode are rounded before refractory metal is deposited for silicidation. This reduces intensive application of film stresses which are generated in heat treatment, enabling formation of a silicide layer with a uniform, sufficient thickness.Type: GrantFiled: May 27, 2011Date of Patent: August 14, 2012Assignee: Panasonic CorporationInventors: Kenshi Kanegae, Akihiko Tsuzumitani, Atsushi Ikeda
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Publication number: 20110227172Abstract: In order that a top surface of a gate electrode does not have sharp portions, ends of the top surface of the gate electrode are rounded before refractory metal is deposited for silicidation. This reduces intensive application of film stresses which are generated in heat treatment, enabling formation of a silicide layer with a uniform, sufficient thickness.Type: ApplicationFiled: May 27, 2011Publication date: September 22, 2011Applicant: Panasonic CorporationInventors: Kenshi Kanegae, Akihiko Tsuzumitani, Atsushi Ikeda
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Patent number: 7973367Abstract: In order that a top surface of a gate electrode does not have sharp portions, ends of the top surface of the gate electrode are rounded before refractory metal is deposited for silicidation. This reduces intensive application of film stresses which are generated in heat treatment, enabling formation of a silicide layer with a uniform, sufficient thickness.Type: GrantFiled: December 30, 2009Date of Patent: July 5, 2011Assignee: Panasonic CorporationInventors: Kenshi Kanegae, Akihiko Tsuzumitani, Atsushi Ikeda
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Patent number: 7879661Abstract: A semiconductor device of a dual-gate structure including a P-channel type field-effect transistor formed at a first region of a substrate and an N-channel type field-effect transistor formed at a second region of the substrate, includes a gate electrode including a polycrystalline silicon film continuously formed on the substrate to cover the first and second regions and a metal silicide film formed on the polycrystalline silicon film. The polycrystalline silicon film has a P-type part located on the first region and an N-type part coming into contact with the P-type part and located on the second region, and the P-type part is further doped with a heavier element than a P-type impurity that determines a conductivity type of the P-type part.Type: GrantFiled: March 7, 2008Date of Patent: February 1, 2011Assignee: Panasonic CorporationInventor: Akihiko Tsuzumitani
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Publication number: 20100102396Abstract: In order that a top surface of a gate electrode does not have sharp portions, ends of the top surface of the gate electrode are rounded before refractory metal is deposited for silicidation. This reduces intensive application of film stresses which are generated in heat treatment, enabling formation of a silicide layer with a uniform, sufficient thickness.Type: ApplicationFiled: December 30, 2009Publication date: April 29, 2010Applicant: PANASONIC CORPORATIONInventors: Kenshi Kanegae, Akihiko Tsuzumitani, Atsushi Ikeda
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Publication number: 20100078730Abstract: A semiconductor device includes a gate electrode. The gate electrode includes a silicide layer obtained by siliciding porous silicon or organic silicon.Type: ApplicationFiled: December 8, 2009Publication date: April 1, 2010Applicant: PANASONIC CORPORATIONInventors: Yoichi YOSHIDA, Akihiko Tsuzumitani, Kenshi Kanegae
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Patent number: 7663191Abstract: In order that a top surface of a gate electrode does not have sharp portions, ends of the top surface of the gate electrode are rounded before refractory metal is deposited for silicidation. This reduces intensive application of film stresses which are generated in heat treatment, enabling formation of a silicide layer with a uniform, sufficient thickness.Type: GrantFiled: July 12, 2005Date of Patent: February 16, 2010Assignee: Panasonic CorporationInventors: Kenshi Kanegae, Akihiko Tsuzumitani, Atsushi Ikeda
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Publication number: 20080166868Abstract: A semiconductor device of a dual-gate structure including a P-channel type field-effect transistor formed at a first region of a substrate and an N-channel type field-effect transistor formed at a second region of the substrate, includes a gate electrode including a polycrystalline silicon film continuously formed on the substrate to cover the first and second regions and a metal silicide film formed on the polycrystalline silicon film. The polycrystalline silicon film has a P-type part located on the first region and an N-type part coming into contact with the P-type part and located on the second region, and the P-type part is further doped with a heavier element than a P-type impurity that determines a conductivity type of the P-type part.Type: ApplicationFiled: March 7, 2008Publication date: July 10, 2008Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventor: Akihiko Tsuzumitani
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Patent number: 7361932Abstract: A semiconductor device of a dual-gate structure including a P-channel type field-effect transistor formed at a first region of a substrate and an N-channel type field-effect transistor formed at a second region of the substrate, includes a gate electrode including a polycrystalline silicon film continuously formed on the substrate to cover the first and second regions and a metal silicide film formed on the polycrystalline silicon film. The polycrystalline silicon film has a P-type part located on the first region and an N-type part coming into contact with the P-type part and located on the second region, and the P-type part is further doped with a heavier element than a P-type impurity that determines a conductivity type of the P-type part.Type: GrantFiled: June 26, 2006Date of Patent: April 22, 2008Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Akihiko Tsuzumitani
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Publication number: 20070138573Abstract: A semiconductor device according to the present invention comprises a silicon substrate, a gate electrode formed on a main surface of the silicon substrate with a gate insulation film therethrough, a sidewall spacer formed so as to cover a side surface of the gate electrode and including at least two layers of a silicon oxide film as a lowermost layer and a silicon nitride film formed thereon, a source region and a drain region formed in the main surface of the silicon substrate so as to sandwich the gate electrode, a protection film formed so as to cover an end surface of the silicon oxide film without extending below said silicon nitride film, the end surface being on a side of said source region and said drain region, and a metal silicide layer formed in the source region and the drain region on a side of said protection film away from said gate electrode.Type: ApplicationFiled: December 1, 2006Publication date: June 21, 2007Applicants: Renesas Technology Corp., Matsushita Electric Industrial Co., Ltd.Inventors: Keiichiro KASHIHARA, Tomonori Okudaira, Tadashi Yamaguchi, Atsushi Ishinaga, Kenshi Kanegae, Akihiko Tsuzumitani
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Patent number: 7202095Abstract: A measurement substrate 100 in which a silicon oxide film 102, a polysilicon layer 103 and a titanium silicide layer 104 are formed over a silicon substrate 101 in this order is prepared. The measurement substrate 100 is irradiated with X-rays so that the proportions of three types of silicides with different compositions in the titanium silicide layer 104 are measured based on the intensity of hard X-rays emitted from oxygen in the silicon oxide film 102 and the intensity of hard X-rays emitted from titanium in the titanium silicide layer 104.Type: GrantFiled: January 7, 2004Date of Patent: April 10, 2007Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Akihiko Tsuzumitani, Yasutoshi Okuno
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Publication number: 20070072371Abstract: A semiconductor device of a dual-gate structure including a P-channel type field-effect transistor formed at a first region of a substrate and an N-channel type field-effect transistor formed at a second region of the substrate, includes a gate electrode including a polycrystalline silicon film continuously formed on the substrate to cover the first and second regions and a metal silicide film formed on the polycrystalline silicon film. The polycrystalline silicon film has a P-type part located on the first region and an N-type part coming into contact with the P-type part and located on the second region, and the P-type part is further doped with a heavier element than a P-type impurity that determines a conductivity type of the P-type part.Type: ApplicationFiled: June 26, 2006Publication date: March 29, 2007Inventor: Akihiko Tsuzumitani
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Publication number: 20060006478Abstract: In order that a top surface of a gate electrode does not have sharp portions, ends of the top surface of the gate electrode are rounded before refractory metal is deposited for silicidation. This reduces intensive application of film stresses which are generated in heat treatment, enabling formation of a silicide layer with a uniform, sufficient thickness.Type: ApplicationFiled: July 12, 2005Publication date: January 12, 2006Inventors: Kenshi Kanegae, Akihiko Tsuzumitani, Atsushi Ikeda
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Patent number: 6916705Abstract: In a memory cell of a DRAM, that is, a semiconductor memory, a bit line connected to a bit line plug and a local interconnect are provided on a first interlayer insulating film. A connection conductor film of TiAlN is provided on the top and side faces of an upper barrier metal and side faces of a Pt film and a BST film. No contact is formed above the Pt film used for forming an upper electrode, and the upper electrode is connected to an upper interconnect (namely, a Cu interconnect) through the connection conductor film, a dummy lower electrode, a dummy cell plug and the local interconnect. Since the Pt film is not exposed to a reducing atmosphere, the characteristic degradation of a capacitor insulating film can be prevented.Type: GrantFiled: September 8, 2003Date of Patent: July 12, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hisashi Ogawa, Yoshihiro Mori, Akihiko Tsuzumitani
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Patent number: 6884674Abstract: A semiconductor device has a capacitance insulating film having a perovskite structure represented by the general formula ABO3 (where each of A and B is a metal element) and first and second electrodes opposed to each other with the capacitance insulating film interposed therebetween. The capacitance insulating film is formed such that the composition of the metal element A or B is higher in the region thereof adjacent the first electrode than in the other region thereof.Type: GrantFiled: February 13, 2003Date of Patent: April 26, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Akihiko Tsuzumitani, Hisashi Ogawa, Yasutoshi Okuno, Yoshihiro Mori
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Patent number: 6784474Abstract: A memory cell in a DRAM, which is a semiconductor memory device, is provided with a bit line 21a connected to a bit line plug 20b and a local interconnect 21b, over a first interlevel insulating film 18. A conductor sidewall 40 of TiAlN is formed on side faces of hard mask 37, upper barrier metal 36, Pt film 35 and BST film 34. No contact hole is provided on the Pt film 35 constituting an upper electrode 35a. The upper electrode 35a is connected to an upper interconnect (a Cu interconnect 42) via the conductor sidewall 40, dummy lower electrode 33b, dummy cell plug 30 and local interconnect 21b. The Pt film 35 is not exposed to a reducing atmosphere, and therefore deterioration in characteristics of the capacitive insulating film 34a can be prevented.Type: GrantFiled: August 8, 2002Date of Patent: August 31, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hisashi Ogawa, Yoshihiro Mori, Akihiko Tsuzumitani
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Patent number: 6773979Abstract: The invention provides a method for fabricating a semiconductor device including a concaved capacitor device having a lower electrode, a capacitor dielectric film of a perovskite type high dielectric constant or ferroelectric material formed on the lower electrode and an upper electrode formed on the capacitor dielectric film. In this method, a step of forming a conducting film to be formed into the lower electrode includes sub-steps of forming a lower conducting film by sputtering on walls and a bottom of a recess formed in an insulating film on a substrate; and forming an upper conducting film on the lower conducting film by CVD.Type: GrantFiled: January 2, 2002Date of Patent: August 10, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Yasutoshi Okuno, Akihiko Tsuzumitani, Yoshihiro Mori
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Publication number: 20040137650Abstract: A measurement substrate 100 in which a silicon oxide film 102, a polysilicon layer 103 and a titanium silicide layer 104 are formed over a silicon substrate 101 in this order is prepared. The measurement substrate 100 is irradiated with X-rays so that the proportions of three types of silicides with different compositions in the titanium silicide layer 104 are measured based on the intensity of hard X-rays emitted from oxygen in the silicon oxide film 102 and the intensity of hard X-rays emitted from titanium in the titanium silicide layer 104.Type: ApplicationFiled: January 7, 2004Publication date: July 15, 2004Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Akihiko Tsuzumitani, Yasutoshi Okuno
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Patent number: 6762445Abstract: In a DRAM memory cell that is a semiconductor memory device, a bit line connected to a bit line plug and local interconnect are provided on a first interlayer insulating film. A contact is not provided on a Pt film constituting an upper electrode, and a dummy lower electrode is in direct contact with a dummy barrier metal. That is, the upper electrode is connected to upper layer interconnect (Cu interconnect) by the dummy lower electrode, a dummy cell plug and the local interconnect. Since the Pt film is not exposed to a reducing atmosphere, deterioration of characteristics of a capacitive insulating film can be prevented.Type: GrantFiled: July 17, 2002Date of Patent: July 13, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hisashi Ogawa, Yoshihiro Mori, Akihiko Tsuzumitani
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Publication number: 20040056294Abstract: In a memory cell of a DRAM, that is, a semiconductor memory, a bit line connected to a bit line plug and a local interconnect are provided on a first interlayer insulating film. A connection conductor film of TiAlN is provided on the top and side faces of an upper barrier metal and side faces of a Pt film and a BST film. No contact is formed above the Pt film used for forming an upper electrode, and the upper electrode is connected to an upper interconnect (namely, a Cu interconnect) through the connection conductor film, a dummy lower electrode, a dummy cell plug and the local interconnect. Since the Pt film is not exposed to a reducing atmosphere, the characteristic degradation of a capacitor insulating film can be prevented.Type: ApplicationFiled: September 8, 2003Publication date: March 25, 2004Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Hisashi Ogawa, Yoshihiro Mori, Akihiko Tsuzumitani