Abstract: A microcomputer capable of outputting pulses in which an arithmetic processing unit outputs pulse control data according to the receiving of a trigger signal transferred from a trigger circuit, a data latch circuit latches each kind of pulse control data to be used for controlling output operation of the control register that stores the pulse control data, the data latch circuit outputs a pulse control signal, a NAND circuit performs a logical arithmetic operation between the output from the pulse generation circuit and the pulse control signal from the data latch circuit, so that a desired pulse or a pulse train is output in real time.

Abstract: In a timer apparatus, the clock controlling circuit thereof outputs a clock signal during a period in which an input signal is significant. The counter thereof counts the number of pulses of the clock signal to generate a count-up signal when the value of count reaches a prescribed value. The initialization circuit thereof outputs an initialization signal when the input is not significant. The clock controlling circuit stops the output of the clock signal when the count-up signal is generated. Thereby, it is prevented to misjudge the detection of an effective pulse width to achieve the effective pulse width though the pulse width of the pulse does not actually reach the effective pulse width actually.

Abstract: An A/D converter wherein data obtained by A/D converting an analog signal in an A/D converting unit is stored in a first register, the data in the first register and the data in a second register are compared to each other by a comparator, and when the data in the first register is larger (or smaller) than that in the second register, a first switching means is closed so that the data in the first register is stored in the second register. In the second register, a maximum value (or a minimum value) of the A/D-converted data hitherto obtained is stored.

Abstract: An A/D converter comprising a plurality of inputs, an input selection array to select one of the input signals, an A/D circuit providing a digital output and a conversion completion signal, a counter for sweeping a contiguous subset of the input channels sequentially, the counter incrementing once each time the conversion completion signal is asserted and resetting to point to the first channel in the subset after reaching the last channel in the subset, a channel memory for storing the value of the counter while an optional channel is selected for conversion without regard to the present position of the sweeping counter, a return bus, activated by the conversion completion signal, for replacing the value of the counter after the optional conversion is complete and returning to the normal sweep sequence in the previous position in the sequence, thereby avoiding useless conversion operations.

Abstract: A serial data input shift register in which an additional register receives the output of the serial shift register. The bits of both registers are initialized to one value except for the input location of the shift register which is initialized to a second value. When the second value reaches the additional register, the shift register has been filled.

Abstract: A parity checker circuit for performing a parity check in the serial transfer of data in an integrated circuit having an odd or even decision circuit receiving sequential bits constituting a data stream and generating an output signal having a level which becomes high or low and representing whether the number of "1" or "0" in the data is odd or even, and a parity flag circuit connected to receive the output signal from the decision circuit and operable in accordance with a write signal received simultaneously with the high or low level output signal and, in response to these signals, for outputting a parity flag indicative of the parity of the data.