Abstract: A first current controlled oscillator outputs an oscillation signal of a first frequency equal to a product of a first control current and a first gain. A first voltage/current converting circuit outputs a first output current equal to a product of a second gain and a voltage difference between a first control voltage and a first reference voltage. A first reference current generator outputs a constant current. A control current circuit outputs a second output current variable. An adder sets the first control current to a sum of the first output current, the constant current and the second output current.

Abstract: A level shift circuit encompasses a first transmission circuit configured to transmit a leading edge of an input signal, a second transmission circuit configured to transmit a trailing edge of the input signal, and a composite circuit configured to generate an output signal by synthesizing the leading edge and the trailing edge.

Abstract: An integrated circuit for testing a PLL circuit that includes a phase error generator to receive a signal gained by dividing an oscillated signal from a voltage controlled oscillator and a reference signal so as to detect a phase error signal between the both, an integrating circuit to integrate error signals outputted by the phase error generation circuit, a reference voltage generator to generate a predetermined reference voltage, and a comparator configured to compare an integration result voltage outputted from the integrating circuit with a reference voltage generated by the reference voltage generation circuit, wherein the reference voltage generator and the comparison circuit is configured electrically outside of a loop in the PLL circuit.

Abstract: A voltage controlled oscillator includes an oscillation controller, first and second current sources, oscillation section, and first and second fluctuation transmitters. The oscillation controller generates first and second control potentials. The first and second current sources generate control currents corresponding to the first and second control potentials, respectively. The oscillation section is connected to a power source potential node via the first current source and connected to a ground potential node via the second current source, and generates a clock. The first fluctuation transmitter is disposed between the power source potential node and the first control potential node, and transmits a potential fluctuation in the power source potential node to the first control potential node.

Abstract: A level shift circuit encompasses a first transmission circuit configured to transmit a leading edge of an input signal, a second transmission circuit configured to transmit a trailing edge of the input signal, and a composite circuit configured to generate an output signal by synthesizing the leading edge and the trailing edge.

Abstract: A first current controlled oscillator outputs an oscillation signal of a first frequency equal to a product of a first control current and a first gain. A first voltage/current converting circuit outputs a first output current equal to a product of a second gain and a voltage difference between a first control voltage and a first reference voltage. A first reference current generator outputs a constant current. A control current circuit outputs a second output current variable. An adder sets the first control current to a sum of the first output current, the constant current and the second output current.

Abstract: An offset compensation circuit comprises an A/D converter, a D/A converter, an attenuator and an analog adder. The A/D converter measures the DC level of an inverting type analog output buffer arranged in an analog signal processing circuit and converts the obtained analog signal into a digital signal. The D/A converter receives the digital signal output from the A/D converter as input and converts the digital signal into an analog signal. The attenuator receives the analog signal output from the D/A converter as input and attenuates its amplitude. The analog adder receives the output signal of the attenuator and that of the analog signal processing circuit as inputs, adds the two signals and supplies the sum signal to the inverting type analog output buffer as input signal of the latter.

Abstract: An offset compensation circuit comprises an A/D converter, a D/A converter, an attenuator and an analog adder. The A/D converter measures the DC level of an inverting type analog output buffer arranged in an analog signal processing circuit and converts the obtained analog signal into a digital signal. The D/A converter receives the digital signal output from the A/D converter as input and converts the digital signal into an analog signal. The attenuator receives the analog signal output from the D/A converter as input and attenuates its amplitude. The analog adder receives the output signal of the attenuator and that of the analog signal processing circuit as inputs, adds the two signals and supplies the sum signal to the inverting type analog output buffer as input signal of the latter.

Abstract: A voltage controlled oscillator includes an oscillation controller, first and second current sources, oscillation section, and first and second fluctuation transmitters. The oscillation controller generates first and second control potentials. The first and second current sources generate control currents corresponding to the first and second control potentials, respectively. The oscillation section is connected to a power source potential node via the first current source and connected to a ground potential node via the second current source, and generates a clock. The first fluctuation transmitter is disposed between the power source potential node and the first control potential node, and transmits a potential fluctuation in the power source potential node to the first control potential node.

Abstract: A voltage-controlled oscillator comprises a level converting circuit, an amplitude controller, a voltage-controlled oscillation section having differential delay cells connected in a ring form, and an output level converting circuit. The level converting circuit has limiters which respectively limit a maximum value and a minimum value of a control current. Those limiters permit only a region where the voltage-controlled oscillation section properly performs its oscillating operation to be used.

Abstract: A delay locked loop has a voltage-controlled delay section and a mis-lock detecting circuit. The voltage-controlled delay sections comprises a plurality of controlled delay circuits, including a specific one. In the mis-lock detecting circuit, there are generated pulse signals, each having a pulse width equivalent to the delay time between the delayed signals output from the adjacent two of the controlled delay circuits preceding the specific controlled delayed circuit. Another pulse signal is generated, which has a pulse width equivalent to the delay time between the delayed signals output from adjacent two of the specific controlled delay circuit and the other controlled delay circuits following the specific one. These pulse signals are added, generating a pulse signal. The number of pulses this pulse signal has per a unit time is compared with the number of pulses a reference signal has per the unit time, thereby detecting whether the delay locked loop is normally locked or not.

Abstract: An integrated circuit disclosed in the present invention comprises a unit for generating an integrated voltage corresponding to a phase error between a reference voltage of a PLL circuit and a dividing signal so as to compare the generated integrated voltage with said reference voltage. With this disclosed structure, it is possible to reduce the test cost and measure the duty value error of the PLL circuit.

Abstract: In a frequency multiplier which generates a multiple output of a reference signal, a reference signal and its inverted signal are propagated through a pair of delay circuits each including a given number of delay cells connected in cascade. The delay cells delay a signal by time t when a control signal is at a high level and delay a signal by time 2t when a control signal is at a low level. The outputs of the delay circuits are added together by an adder circuit to generate a multiple output without using a low-pass filter but by non-feedback control.

Abstract: A voltage controlled oscillator includes plural cascade-connected unit circuits supplied with selection signals corresponding to an oscillation frequency. Each unit circuit includes a voltage controlled delay circuit, selection circuit and adder circuit. The selection circuit has a first input terminal supplied with an output signal of the voltage controlled delay circuit and a second input terminal supplied with the selection signal. The adder circuit has a first input terminal supplied with an output signal of the selection circuit, a second input terminal supplied with a feedback signal from a next-stage one of the unit circuits and a third input terminal supplied with the selection signal. The adder circuit adds signals supplied to its first and second input terminals to form a feedback signal. The output signal of the voltage controlled delay circuit in each unit circuit is supplied to the voltage controlled delay circuit in the next-stage one of the unit circuits.

Abstract: A digital-to-analog converter has a first digital-to-analog converter for M bits, for receiving M high order bits of input data of N bits, and then outputting a predetermined analog output, and a second digital-to-analog converter for (N-M) bits, for receiving (N-M) low order bits of the input data, and then outputting a predetermined analog output. An attenuator attenuates the analog output of the second digital-to-analog converter to 1/2.sup.M. An analog operating circuit adds the analog output of the first digital-to-analog converter and the attenuated analog output of the second digital-to-analog converter, and outputs an analog output as a result of addition of those analog outputs.

Abstract: An object is to keep the oscillation gain nearly constant and attain an oscillation frequency with high stability and low jitter. A voltage controlled oscillator circuit (VCO) is constructed by a VCO control circuit and a ring oscillator. The VCO control circuit has two input terminals (n input, w input). The VC control circuit multiplies the n input by the w input, and outputs a control signal (PMOS n input, NMOS n input) obtained by adding the result of multiplication to the n input. The ring oscillator is constructed by delay circuits of an odd number of stages serially connected.

Abstract: A frequency multiplying circuit includes a plurality of frequency multipliers in a series array. The multiplying ratio of the initial stage frequency multiplier is the greatest compared with the remaining frequency multiplier or multipliers. Further, at least one of the frequency multipliers uses a voltage controlled delay circuit.

Abstract: A voltage controlled delay circuit is comprised of a plurality of stages of delay cells and produces a 2N number of signals delayed behind a reference signal in units of time corresponding to 1/2N the delay time between the reference signal supplied to an input terminal of a first stage delay cell and a signal output from a final stage delay cell. A phase coincidence is achieved between the reference signal and the output signal from the final stage delay cell by a loop including a phase comparator, lowpass filter and voltage controlled delay circuit. An N multiplying logic circuit produces an N multiplied signal from the reference signal with only falls or rises of 2N delay signals.

Abstract: A phase-locked loop (PLL) system including a voltage-controlled oscillator, a divider, a phase detector, and a low-pass filter. The voltage-controlled oscillator has two control input terminals S and L and generates a pulse signal having an oscillation frequency fout2. The divider generates a pulse signal having a frequency fout2/N2 from the output signal of the oscillator. The phase detector detects the phase difference between the pulse signal output from the divider and the a pulse signal having a reference frequency fref and generates an error signal corresponding to the phase difference detected. The low-pass filter integrates the error signal. The output signal of the low-pass filter is input to the control input terminal S of the oscillator. A control signal is input to the control input terminal L of the oscillator to control the free-running frequency of the oscillator.

Abstract: An optical pick-up head for reading writing information from on a magneto-optical record medium including a semiconductor laser, a multi-image plane parallel plate for separating an incident light beam emitted by the semiconductor laser from a return light beam reflected by the optical record medium and dividing the return beam transmitted through and refracted by the multi-image plane parallel plate into a plurality of return light beams, and a signal detecting photodetector receiving a plurality of return light beams, wherein the multi-image plane parallel plate is formed by first and second prisms made of birefringent material and is arranged such that major and minor axes of astigmatism introduced by the plane parallel plate are inclined by 45.degree. with respect to an information track.