Patents by Inventor Akihiro GORYU

Akihiro GORYU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11156654
    Abstract: A semiconductor device inspection apparatus according to embodiments comprises: an action unit that generates an internal stress in a predetermined direction in a semiconductor device; a stress controller that controls a magnitude of the internal stress generated in the semiconductor device by the action unit; a probe electrically connected to the semiconductor device; a probe controller that supplies a current to the semiconductor device via the probe; and a controller that screens the semiconductor device based on a first current flowing through the semiconductor device via the probe while the internal stress is not generated in the semiconductor device and a second current flowing through the semiconductor device via the probe while the action unit generates the internal stress in the semiconductor device.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: October 26, 2021
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Akihiro Goryu, Mitsuaki Kato, Akira Kano, Kenji Hirohata
  • Publication number: 20210293638
    Abstract: An analysis apparatus of an embodiment includes one or more processors. The processors receive structural information indicating a structure of a pipe to be analyzed and fluid information indicating a state of a fluid flowing in the pipe. The one or more processors obtain a plurality of loss factors of the pipe based on the structural information and the fluid information and calculate a wall shear stress of the pipe from the loss factors.
    Type: Application
    Filed: August 27, 2020
    Publication date: September 23, 2021
    Applicants: KABUSHIKI KAISHA TOSHIBA, CANON MEDICAL SYSTEMS CORPORATION
    Inventors: Mitsuaki KATO, Kenji HIROHATA, Akira KANO, Akihiro GORYU
  • Publication number: 20210296279
    Abstract: A semiconductor device 10 includes a pair of electrodes 16 and a conductive connection member 21 electrically bonded to the pair of electrodes 16. At least a portion of a perimeter of a bonding surface 24 of at least one of the pair of electrodes 16 and the conductive connection member 21 includes an electromigration reducing area 22.
    Type: Application
    Filed: August 28, 2020
    Publication date: September 23, 2021
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Mitsuaki KATO, Takahiro OMORI, Akihiro GORYU, Tomoya FUMIKURA, Kenji HIROHATA, Tetsuya KUGIMIYA
  • Patent number: 11079427
    Abstract: An inspection device comprises: a detecting unit that is connected to a plurality of semiconductor chips having mutually different rates of change of electrical resistance with respect to stress loading direction, and that detects an electrical resistance value of each semiconductor chip from electric current flowing in each semiconductor chip; a first memory unit that is used to hold model data meant for converting an electrical resistance value into a characteristic value indicating at least either temperature, or stress, or strain; a converting unit that converts the electrical resistance value of each semiconductor chip as detected by the detecting unit into the characteristic value using the model data held in the first memory unit; and a second memory unit that is used to store the characteristic value, which is obtained by conversion by the converting unit, as time-series data for each of the plurality of semiconductor chips.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: August 3, 2021
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Mitsuaki Kato, Akihiro Goryu, Kenji Hirohata
  • Patent number: 11018227
    Abstract: A semiconductor storage device comprises a plurality of memory cells arranged in a matrix. Each of the memory cells includes: a semiconductor storage element including a silicon carbide substrate and a silicon carbide film on a first surface of the silicon carbide substrate; a lower electrode on a second surface facing away from the first surface of the silicon carbide substrate; and an upper electrode on at least part of a surface of the silicon carbide film, the surface facing away from another surface of the silicon carbide film in contact with the silicon carbide substrate. Each memory cell includes at least one basal plane dislocation formed at at least part of the semiconductor storage element.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: May 25, 2021
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Akihiro Goryu, Akira Kano, Kenji Hirohata
  • Patent number: 10861941
    Abstract: According to an embodiment, in a semiconductor device, a total value of a change amount of chemical potential of the semiconductor device with respect to a expansion direction of a stacking fault and the stacking fault energy of the stacking fault is zero or more.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: December 8, 2020
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akira Kano, Akihiro Goryu, Kenji Hirohata
  • Patent number: 10847620
    Abstract: A semiconductor device comprises a semiconductor chip and a mounting substrate. The semiconductor chip has an element structure including: a silicon carbide substrate that has a hexagonal crystal structure; a gate electrode that is disposed on a part above a first surface corresponding to a (0001) plane or a (000-1) plane of the silicon carbide substrate; an insulating film that is interposed between the silicon carbide substrate and the gate electrode; and a source and a drain that are disposed with respect to the silicon carbide substrate and the gate electrode such that at least a part of a channel through which a carrier moves extends in a <1-100> direction of crystal orientation of the silicon carbide substrate. The mounting substrate is fixed with the semiconductor chip such that compressive stress in a <11-20> direction of crystal orientation of the silicon carbide substrate is applied to the semiconductor chip at least in operation.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: November 24, 2020
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akihiro Goryu, Mitsuaki Kato, Kenji Hirohata
  • Publication number: 20200075733
    Abstract: According to an embodiment, in a semiconductor device, a total value of a change amount of chemical potential of the semiconductor device with respect to a expansion direction of a stacking fault and the stacking fault energy of the stacking fault is zero or more.
    Type: Application
    Filed: February 27, 2019
    Publication date: March 5, 2020
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Akira Kano, Akihiro Goryu, Kenji Hirohata
  • Publication number: 20190288072
    Abstract: A semiconductor storage device comprises a plurality of memory cells arranged in a matrix. Each of the memory cells includes: a semiconductor storage element including a silicon carbide substrate and a silicon carbide film on a first surface of the silicon carbide substrate; a lower electrode on a second surface facing away from the first surface of the silicon carbide substrate; and an upper electrode on at least part of a surface of the silicon carbide film, the surface facing away from another surface of the silicon carbide film in contact with the silicon carbide substrate. Each memory cell includes at least one basal plane dislocation formed at at least part of the semiconductor storage element.
    Type: Application
    Filed: August 30, 2018
    Publication date: September 19, 2019
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Akihiro Goryu, Akira Kano, Kenji Hirohata
  • Publication number: 20190219628
    Abstract: An inspection device comprises: a detecting unit that is connected to a plurality of semiconductor chips having mutually different rates of change of electrical resistance with respect to stress loading direction, and that detects an electrical resistance value of each semiconductor chip from electric current flowing in each semiconductor chip; a first memory unit that is used to hold model data meant for converting an electrical resistance value into a characteristic value indicating at least either temperature, or stress, or strain; a converting unit that converts the electrical resistance value of each semiconductor chip as detected by the detecting unit into the characteristic value using the model data held in the first memory unit; and a second memory unit that is used to store the characteristic value, which is obtained by conversion by the converting unit, as time-series data for each of the plurality of semiconductor chips.
    Type: Application
    Filed: August 30, 2018
    Publication date: July 18, 2019
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Mitsuaki KATO, Akihiro Goryu, Kenji Hirohata
  • Publication number: 20190221646
    Abstract: A semiconductor device comprises a semiconductor chip and a mounting substrate. The semiconductor chip has an element structure including: a silicon carbide substrate that has a hexagonal crystal structure; a gate electrode that is disposed on a part above a first surface corresponding to a (0001) plane or a (000-1) plane of the silicon carbide substrate; an insulating film that is interposed between the silicon carbide substrate and the gate electrode; and a source and a drain that are disposed with respect to the silicon carbide substrate and the gate electrode such that at least a part of a channel through which a carrier moves extends in a <1-100> direction of crystal orientation of the silicon carbide substrate. The mounting substrate is fixed with the semiconductor chip such that compressive stress in a <11-20> direction of crystal orientation of the silicon carbide substrate is applied to the semiconductor chip at least in operation.
    Type: Application
    Filed: August 30, 2018
    Publication date: July 18, 2019
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Akihiro GORYU, Mitsuaki Kato, Kenji Hirohata
  • Publication number: 20190064248
    Abstract: A semiconductor device inspection apparatus according to embodiments comprises: an action unit that generates an internal stress in a predetermined direction in a semiconductor device; a stress controller that controls a magnitude of the internal stress generated in the semiconductor device by the action unit; a probe electrically connected to the semiconductor device; a probe controller that supplies a current to the semiconductor device via the probe; and a controller that screens the semiconductor device based on a first current flowing through the semiconductor device via the probe while the internal stress is not generated in the semiconductor device and a second current flowing through the semiconductor device via the probe while the action unit generates the internal stress in the semiconductor device.
    Type: Application
    Filed: March 5, 2018
    Publication date: February 28, 2019
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Akihiro GORYU, Mitsuaki Kato, Akira Kano, Kenji Hirohata
  • Patent number: 10206587
    Abstract: An image processing apparatus according to an embodiment includes a processing circuitry. The processing circuitry is configured to obtain images in a time series including images of a blood vessel of a subject and correlation information indicating a correlational relationship between physical indices of the blood vessel and function indices of the blood vessel related to vascular hemodynamics, calculate blood vessel morphology indices in a time series indicating morphology of the blood vessel of the subject, on a basis of the images in the time series, and identify a function index of the blood vessel of the subject, by using a physical index of the blood vessel of the subject obtained from the blood vessel morphology indices, on a basis of the correlation information.
    Type: Grant
    Filed: November 4, 2016
    Date of Patent: February 19, 2019
    Assignee: Toshiba Medical Systems Corporation
    Inventors: Akira Kano, Kenji Hirohata, Junichiro Ooga, Mitsuaki Kato, Takuya Hongo, Akihiro Goryu, Shigeo Kaminaga, Yasuko Fujisawa, Satoshi Wakai, Yoshihiro Ikeda, Kazumasa Arakita
  • Publication number: 20180266967
    Abstract: According to one embodiment, as optical test apparatus includes a pump beam generating unit, a probe beam generating unit; and a photodetector. The pump beam generating unit generates a pump beam for exciting an elastic wave in a specimen. The probe beam generating unit generates a probe beam. The photodetector receives the probe beam. A first light penetration depth of the probe beam relative to the specimen is longer than a second light penetration depth of the pump beam relative to the specimen.
    Type: Application
    Filed: August 31, 2017
    Publication date: September 20, 2018
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hiroshi OHNO, Akihiro GORYU, Mitsuaki KATO, Hiroya KANO, Hideaki OKANO
  • Publication number: 20180112884
    Abstract: According to one embodiment, a heat exchanger includes a pipe through which a fluid flows, and a supply device that supplies the fluid to the pipe. The pipe includes a flexible part deformed by flowing of the fluid, and a constricted part located at a downstream side of the flexible part along a flow direction of the fluid.
    Type: Application
    Filed: August 28, 2017
    Publication date: April 26, 2018
    Inventors: Akihiro GORYU, Takuya HONGO, Mitsuaki KATO, Akira KANO, Kenji HOROHATA
  • Publication number: 20170071479
    Abstract: An image processing apparatus according to an embodiment includes a processing circuitry. The processing circuitry is configured to obtain images in a time series including images of a blood vessel of a subject and correlation information indicating a correlational relationship between physical indices of the blood vessel and function indices of the blood vessel related to vascular hemodynamics, calculate blood vessel morphology indices in a time series indicating morphology of the blood vessel of the subject, on a basis of the images in the time series, and identify a function index of the blood vessel of the subject, by using a physical index of the blood vessel of the subject obtained from the blood vessel morphology indices, on a basis of the correlation information.
    Type: Application
    Filed: November 4, 2016
    Publication date: March 16, 2017
    Applicant: Toshiba Medical Systems Corporation
    Inventors: Akira KANO, Kenji HIROHATA, Junichiro OOGA, Mitsuaki KATO, Takuya HONGO, Akihiro GORYU, Shigeo KAMINAGA, Yasuko FUJISAWA, Satoshi WAKAI, Yoshihiro IKEDA, Kazumasa ARAKITA
  • Publication number: 20150327780
    Abstract: An image processing apparatus according to an embodiment includes a processing circuitry. The processing circuitry is configured to obtain images in a time series including images of a blood vessel of a subject and correlation information indicating a correlational relationship between physical indices of the blood vessel and function indices of the blood vessel related to vascular hemodynamics, calculate blood vessel morphology indices in a time series indicating morphology of the blood vessel of the subject, on a basis of the images in the time series, and identify a function index of the blood vessel of the subject, by using a physical index of the blood vessel of the subject obtained from the blood vessel morphology indices, on a basis of the correlation information.
    Type: Application
    Filed: May 15, 2015
    Publication date: November 19, 2015
    Applicants: Kabushiki Kaisha Toshiba, Toshiba Medical Systems Corporation
    Inventors: Akira KANO, Kenji HIROHATA, Junichiro OOGA, Mitsuaki KATO, Takuya HONGO, Akihiro GORYU, Shigeo KAMINAGA, Yasuko FUJISAWA, Satoshi WAKAI, Yoshihiro IKEDA, Kazumasa ARAKITA