Abstract: An information processing apparatus according to one embodiment, comprising: a regression model generator configured to, by combining two or more of a plurality of variables, generate a plurality of terms that include combinations of two or more of the plurality of variables, respectively, and generate a regression model that regresses a property variable or an objective variable indicating an output of an objective function that includes the property variable, by the plurality of terms; a subgroup generator configured to generate, based on coefficients of the plurality of terms included in the regression model, subgroups that are the combinations of variables included the terms, respectively; and a subspace search processor configured to perform search for each of subspaces spanned by the subgroups based on an optimization criterion for the objective function, and generate pieces of first design value data that include values of the plurality of variables for the subspaces.

Abstract: According to one embodiment, a semiconductor device includes first to third electrodes, a first conductive member, a semiconductor member, and a first insulating member. The third electrode includes a third electrode end portion and a third electrode other-end portion. The first conductive member includes a first conductive member end portion and a first conductive member other-end portion. The first conductive member is electrically connected with one of the second electrode or the third electrode. The semiconductor member includes first to fourth semiconductor regions. The first semiconductor region includes first and second partial regions. The third semiconductor region is electrically connected with the second electrode. The fourth semiconductor region is electrically connected with the first electrode. At least a portion of the first insulating member is between the semiconductor member and the third electrode and between the semiconductor member and the first conductive member.

Abstract: According to one embodiment, a semiconductor device includes first to third electrodes, a conductive member, a semiconductor member, and an insulating member. The conductive member includes a conductive member end portion and a conductive member other-end portion. The conductive member end portion is between the first electrode and the conductive member other-end portion. The conductive member is electrically connected with one of the second electrode or the third electrode. The semiconductor member includes first to third semiconductor regions. The first semiconductor region includes first and second partial regions. The first partial region is between the first and second electrodes. The second semiconductor region is between the first partial region and the third semiconductor region. The third semiconductor region is electrically connected with the second electrode.

Abstract: According to one embodiment, a semiconductor device includes first to third electrodes, a first conductive member, a semiconductor member, and a first insulating member. The third electrode includes a third electrode end portion and a third electrode other-end portion. The first conductive member includes a first conductive member end portion and a first conductive member other-end portion. The first conductive member is electrically connected with one of the second electrode or the third electrode. The semiconductor member includes first to fourth semiconductor regions. The first semiconductor region includes first and second partial regions. The third semiconductor region is electrically connected with the second electrode. The fourth semiconductor region is electrically connected with the first electrode. At least a portion of the first insulating member is between the semiconductor member and the third electrode and between the semiconductor member and the first conductive member.

Abstract: A semiconductor device inspection apparatus according to embodiments comprises: an action unit that generates an internal stress in a predetermined direction in a semiconductor device; a stress controller that controls a magnitude of the internal stress generated in the semiconductor device by the action unit; a probe electrically connected to the semiconductor device; a probe controller that supplies a current to the semiconductor device via the probe; and a controller that screens the semiconductor device based on a first current flowing through the semiconductor device via the probe while the internal stress is not generated in the semiconductor device and a second current flowing through the semiconductor device via the probe while the action unit generates the internal stress in the semiconductor device.

Abstract: A semiconductor device 10 includes a pair of electrodes 16 and a conductive connection member 21 electrically bonded to the pair of electrodes 16. At least a portion of a perimeter of a bonding surface 24 of at least one of the pair of electrodes 16 and the conductive connection member 21 includes an electromigration reducing area 22.

Abstract: An analysis apparatus of an embodiment includes one or more processors. The processors receive structural information indicating a structure of a pipe to be analyzed and fluid information indicating a state of a fluid flowing in the pipe. The one or more processors obtain a plurality of loss factors of the pipe based on the structural information and the fluid information and calculate a wall shear stress of the pipe from the loss factors.

Abstract: An inspection device comprises: a detecting unit that is connected to a plurality of semiconductor chips having mutually different rates of change of electrical resistance with respect to stress loading direction, and that detects an electrical resistance value of each semiconductor chip from electric current flowing in each semiconductor chip; a first memory unit that is used to hold model data meant for converting an electrical resistance value into a characteristic value indicating at least either temperature, or stress, or strain; a converting unit that converts the electrical resistance value of each semiconductor chip as detected by the detecting unit into the characteristic value using the model data held in the first memory unit; and a second memory unit that is used to store the characteristic value, which is obtained by conversion by the converting unit, as time-series data for each of the plurality of semiconductor chips.

Abstract: A semiconductor storage device comprises a plurality of memory cells arranged in a matrix. Each of the memory cells includes: a semiconductor storage element including a silicon carbide substrate and a silicon carbide film on a first surface of the silicon carbide substrate; a lower electrode on a second surface facing away from the first surface of the silicon carbide substrate; and an upper electrode on at least part of a surface of the silicon carbide film, the surface facing away from another surface of the silicon carbide film in contact with the silicon carbide substrate. Each memory cell includes at least one basal plane dislocation formed at at least part of the semiconductor storage element.

Abstract: According to an embodiment, in a semiconductor device, a total value of a change amount of chemical potential of the semiconductor device with respect to a expansion direction of a stacking fault and the stacking fault energy of the stacking fault is zero or more.

Abstract: A semiconductor device comprises a semiconductor chip and a mounting substrate. The semiconductor chip has an element structure including: a silicon carbide substrate that has a hexagonal crystal structure; a gate electrode that is disposed on a part above a first surface corresponding to a (0001) plane or a (000-1) plane of the silicon carbide substrate; an insulating film that is interposed between the silicon carbide substrate and the gate electrode; and a source and a drain that are disposed with respect to the silicon carbide substrate and the gate electrode such that at least a part of a channel through which a carrier moves extends in a <1-100> direction of crystal orientation of the silicon carbide substrate. The mounting substrate is fixed with the semiconductor chip such that compressive stress in a <11-20> direction of crystal orientation of the silicon carbide substrate is applied to the semiconductor chip at least in operation.

Abstract: According to an embodiment, in a semiconductor device, a total value of a change amount of chemical potential of the semiconductor device with respect to a expansion direction of a stacking fault and the stacking fault energy of the stacking fault is zero or more.

Abstract: A semiconductor storage device comprises a plurality of memory cells arranged in a matrix. Each of the memory cells includes: a semiconductor storage element including a silicon carbide substrate and a silicon carbide film on a first surface of the silicon carbide substrate; a lower electrode on a second surface facing away from the first surface of the silicon carbide substrate; and an upper electrode on at least part of a surface of the silicon carbide film, the surface facing away from another surface of the silicon carbide film in contact with the silicon carbide substrate. Each memory cell includes at least one basal plane dislocation formed at at least part of the semiconductor storage element.

Abstract: An inspection device comprises: a detecting unit that is connected to a plurality of semiconductor chips having mutually different rates of change of electrical resistance with respect to stress loading direction, and that detects an electrical resistance value of each semiconductor chip from electric current flowing in each semiconductor chip; a first memory unit that is used to hold model data meant for converting an electrical resistance value into a characteristic value indicating at least either temperature, or stress, or strain; a converting unit that converts the electrical resistance value of each semiconductor chip as detected by the detecting unit into the characteristic value using the model data held in the first memory unit; and a second memory unit that is used to store the characteristic value, which is obtained by conversion by the converting unit, as time-series data for each of the plurality of semiconductor chips.

Abstract: A semiconductor device comprises a semiconductor chip and a mounting substrate. The semiconductor chip has an element structure including: a silicon carbide substrate that has a hexagonal crystal structure; a gate electrode that is disposed on a part above a first surface corresponding to a (0001) plane or a (000-1) plane of the silicon carbide substrate; an insulating film that is interposed between the silicon carbide substrate and the gate electrode; and a source and a drain that are disposed with respect to the silicon carbide substrate and the gate electrode such that at least a part of a channel through which a carrier moves extends in a <1-100> direction of crystal orientation of the silicon carbide substrate. The mounting substrate is fixed with the semiconductor chip such that compressive stress in a <11-20> direction of crystal orientation of the silicon carbide substrate is applied to the semiconductor chip at least in operation.

Abstract: A semiconductor device inspection apparatus according to embodiments comprises: an action unit that generates an internal stress in a predetermined direction in a semiconductor device; a stress controller that controls a magnitude of the internal stress generated in the semiconductor device by the action unit; a probe electrically connected to the semiconductor device; a probe controller that supplies a current to the semiconductor device via the probe; and a controller that screens the semiconductor device based on a first current flowing through the semiconductor device via the probe while the internal stress is not generated in the semiconductor device and a second current flowing through the semiconductor device via the probe while the action unit generates the internal stress in the semiconductor device.

Abstract: An image processing apparatus according to an embodiment includes a processing circuitry. The processing circuitry is configured to obtain images in a time series including images of a blood vessel of a subject and correlation information indicating a correlational relationship between physical indices of the blood vessel and function indices of the blood vessel related to vascular hemodynamics, calculate blood vessel morphology indices in a time series indicating morphology of the blood vessel of the subject, on a basis of the images in the time series, and identify a function index of the blood vessel of the subject, by using a physical index of the blood vessel of the subject obtained from the blood vessel morphology indices, on a basis of the correlation information.

Abstract: According to one embodiment, as optical test apparatus includes a pump beam generating unit, a probe beam generating unit; and a photodetector. The pump beam generating unit generates a pump beam for exciting an elastic wave in a specimen. The probe beam generating unit generates a probe beam. The photodetector receives the probe beam. A first light penetration depth of the probe beam relative to the specimen is longer than a second light penetration depth of the pump beam relative to the specimen.

Abstract: According to one embodiment, a heat exchanger includes a pipe through which a fluid flows, and a supply device that supplies the fluid to the pipe. The pipe includes a flexible part deformed by flowing of the fluid, and a constricted part located at a downstream side of the flexible part along a flow direction of the fluid.

Abstract: An image processing apparatus according to an embodiment includes a processing circuitry. The processing circuitry is configured to obtain images in a time series including images of a blood vessel of a subject and correlation information indicating a correlational relationship between physical indices of the blood vessel and function indices of the blood vessel related to vascular hemodynamics, calculate blood vessel morphology indices in a time series indicating morphology of the blood vessel of the subject, on a basis of the images in the time series, and identify a function index of the blood vessel of the subject, by using a physical index of the blood vessel of the subject obtained from the blood vessel morphology indices, on a basis of the correlation information.