Abstract: A first aspect of the present invention is carbon fiber wherein the surface of a monofilament has a center line average roughness Ra of 6.0 nm or more and 13 nm or less, and the monofilament has a long diameter/short diameter ratio of 1.11 or more and 1.245 or less. A second aspect of the present invention is carbon fiber precursor acrylic fiber wherein the surface of a monofilament has a center line average roughness Ra of 18 nm or more and 27 nm or less, and the monofilament has a long diameter/short diameter ratio of 1.11 or more and 1.245 or less. The carbon fiber according to the first aspect is obtained by stabilizing and carbonizing under specific conditions the carbon fiber precursor acrylic fiber according to the second aspect.

Abstract: A semiconductor memory device is provided with a row control circuit, in order to dissolve a Row Hammer issue. The row control circuit is configured to: (A) latches one of (a) a target address upon issuing of an ACTIVE command to the semiconductor memory device, and (b) a row address of a victim cell in which data of a memory cell is affected by the target address, as a victim address by using a predetermined row address latch method; and then, (B) refreshes the victim cell having the victim address by a predetermined refresh method upon issuing of a REFRESH command.

Abstract: A semiconductor memory device is provided with a row control circuit, in order to dissolve a Row Hammer issue. The row control circuit is configured to: (A) latches one of (a) a target address upon issuing of an ACTIVE command to the semiconductor memory device, and (b) a row address of a victim cell in which data of a memory cell is affected by the target address, as a victim address by using a predetermined row address latch method; and then, (B) refreshes the victim cell having the victim address by a predetermined refresh method upon issuing of a REFRESH command.

Abstract: An outrigger is connected to a front end part of an apron upper member, and further, is extended from its connected part up to that area of a front side member which is on its front end side and on its outer side in a vehicle width direction so as to be connected to the front side member. One end part of a connecting support member is connected to a connecting portion between the outrigger and the apron upper member. The connecting support member extends inward in the vehicle width direction in a plan view of a vehicle from its connected part, so as to be connected to the front side member.

Abstract: An outrigger is connected to a front end part of an apron upper member, and further, is extended from its connected part up to that area of a front side member which is on its front end side and on its outer side in a vehicle width direction so as to be connected to the front side member. One end part of a connecting support member is connected to a connecting portion between the outrigger and the apron upper member. The connecting support member extends inward in the vehicle width direction in a plan view of a vehicle from its connected part, so as to be connected to the front side member.

Abstract: A semiconductor memory apparatus performs a selection in a normal readout/write-in mode and an automatic refreshing mode and includes a sense amplifier reading out data from a memory device, a first switching device connecting a first power supply voltage acting as an overdrive voltage to a first power supply intermediate node during a first period and then connecting a second power supply voltage acting as an array voltage to the first power supply intermediate node, a second switching device connecting the fourth power supply voltage to a second power supply intermediate node of the sense amplifier when the sense amplifier is driven, a first capacitor connected to the overdrive voltage and charging it, a third switching device switched on in the automatic refreshing mode, and a voltage generator generating a third power supply voltage and applying it and the first power supply voltage in parallel through the third switching device.

Abstract: A vehicle drive battery attachment structure including a battery case disposed at the vehicle rear of a vehicle cabin, a rear side member that is provided at a side portion of a vehicle body rear section and extends along a vehicle front-rear direction, and a bracket that is fixed to the battery case, that includes a low strength portion and a high strength portion in a row along the vehicle front-rear direction, that is fixed to the rear side member at both vehicle front-rear direction end sides of the low strength portion and the high strength portion respectively, and in which the low strength portion is set with lower strength with respect to vehicle front-rear direction load than the high strength portion.

Abstract: There is provided a vehicle front portion structure including: a front side member including a linear portion that extends along the vehicle front and rear direction on the vehicle width direction outside of the vehicle front portion and is disposed on the vehicle front side of a dash panel, and a slanted portion that extends obliquely downward along an undersurface of the dash panel from a rear end portion of the linear portion; and a side portion weak portion disposed in a vehicle width direction outside surface or a vehicle width direction inside surface of the linear portion along a joint between the linear portion and the slanted portion.

Abstract: A vehicle drive battery attachment structure including a battery case disposed at the vehicle rear of a vehicle cabin, a rear side member that is provided at a side portion of a vehicle body rear section and extends along a vehicle front-rear direction, and a bracket that is fixed to the battery case, that includes a low strength portion and a high strength portion in a row along the vehicle front-rear direction, that is fixed to the rear side member at both vehicle front-rear direction end sides of the low strength portion and the high strength portion respectively, and in which the low strength portion is set with lower strength with respect to vehicle front-rear direction load than the high strength portion.

Abstract: There is provided a vehicle front portion structure including: a front side member including a linear portion that extends along the vehicle front and rear direction on the vehicle width direction outside of the vehicle front portion and is disposed on the vehicle front side of a dash panel, and a slanted portion that extends obliquely downward along an undersurface of the dash panel from a rear end portion of the linear portion; and a side portion weak portion disposed in a vehicle width direction outside surface or a vehicle width direction inside surface of the linear portion along a joint between the linear portion and the slanted portion.

Abstract: In a vehicle battery mounting structure, each sidewall of a bracket body has a load-receiving portion extending obliquely from the vehicle vertical direction upper end of a base portion toward the vehicle vertical direction lower end of a flat wall. The load-receiving portion is located between a rear wall and an intermediate beam. Thus, when the intermediate beam is moving toward the vehicle longitudinal direction front side during a rear collision, or the like, a front wall of the intermediate beam smashes against the load-receiving portion.

Abstract: An internal power source voltage generating circuit of a semiconductor memory and a corresponding method shorten an access delay upon transition of a data reading operation in an address period shorter than a prescribed minimum period to an operation in the prescribed minimum period. While a boosted voltage of an external power source voltage is supplied to the semiconductor memory as the internal power source voltage via an output line connected to one end of a condenser. A reference low potential is applied to the other end of the condenser and the external power source voltage is applied to the output line, thereby charging the condenser. If the internal power source voltage is lower than a threshold voltage, the internal power source voltage on the output line is boosted by applying the external power source voltage to the other end of the condenser.

Abstract: An internal pulse waveform shaping circuit provided to an IC chip generates an internal pulse monitor signal that changes in a predetermined direction at a rise timing of an internal pulse signal during a period in which a first enable signal is asserted and a second enable signal is de-asserted and then continues in the changed state for a predetermined period of time or longer, and generates the internal pulse monitor signal that changes in the predetermined direction at a fall timing of the pulse signal during a period in which the first enable signal is de-asserted and the second enable signal is asserted and then continues in the changed state for the predetermined period of time or longer. The generated internal pulse monitor signal is output to a tester for detecting the pulse width of the internal pulse signal.

Abstract: In a vehicle battery mounting structure, each sidewall of a bracket body has a load-receiving portion extending obliquely from the vehicle vertical direction upper end of a base portion toward the vehicle vertical direction lower end of a flat wall. The load-receiving portion is located between a rear wall and an intermediate beam. Thus, when the intermediate beam is moving toward the vehicle longitudinal direction front side during a rear collision, or the like, a front wall of the intermediate beam smashes against the load-receiving portion.

Abstract: An internal power source voltage generating circuit of a semiconductor memory and a corresponding method shorten an access delay upon transition of a data reading operation in an address period shorter than a prescribed minimum period to an operation in the prescribed minimum period. While a boosted voltage of an external power source voltage is supplied to the semiconductor memory as the internal power source voltage via an output line connected to one end of a condenser. A reference low potential is applied to the other end of the condenser and the external power source voltage is applied to the output line, thereby charging the condenser. If the internal power source voltage is lower than a threshold voltage, the internal power source voltage on the output line is boosted by applying the external power source voltage to the other end of the condenser.

Abstract: There is provided a reference potential generating circuit of a semiconductor memory, including: a first MOS transistor group that includes a plurality of first MOS transistors that are connected in series; a second MOS transistor that is connected in series to the first MOS transistor group; a third MOS transistor that is connected in parallel to the circuit in which the first MOS transistor group and the second MOS transistor are connected in series, has a gate connected to a connection point of the first MOS transistor group and the second MOS transistor, and corrects a reference potential from a connection point of the first MOS transistors; and a fourth MOS transistor that is connected to the gate of the third MOS transistor, and decreases the potential of the gate of the third MOS transistor when a permission signal to supply power to the semiconductor memory is input.

Abstract: There is provided a start-up circuit of an internal power supply of a semiconductor memory, including: an odd number of inverters that are connected in series and output a signal indicating whether or not to start to supply power from an internal power supply circuit of the semiconductor memory to an internal power supply circuit, and a discharge unit that is connected to an output side of an inverter at an odd-numbered stage and discharges charges remaining at the connection point between the inverter at the odd-numbered stage and the inverter at the stage immediately thereafter, after supply of power to operate the inverters is stopped.

Abstract: The present invention provides a semiconductor testing apparatus and method capable of reliably determining whether a semiconductor memory is good or bad. A “1” reading test of each cell corresponding to one bit at a first step is first performed on a memory cell array. “0” writing of each cell corresponding to one bit at a second step and a “0” reading test of each cell corresponding to one bit at a third step are executed on the memory cell array. Thus, the time taken from the supply of power to the start of the “0” reading test of the reference cell at the third step can be significantly shortened. As a result, a defect of a reference bit line due to a breaking or high resistance of a gate of a reference column switch transistor corresponding to a normally ON transistor can be screened.

Abstract: An internal power supply control circuit of a semiconductor memory includes a periodic signal generating unit that generates a periodic signal to generate a permission signal to intermittently permit supply of power from an internal power supply circuit of the semiconductor memory to an internal circuit thereof with a predetermined period, when a mode changes from a normal operation mode where power is always supplied from the internal power supply circuit to the internal circuit to a standby mode where consumption power is further suppressed as compared with consumption power in the normal operation mode, and a permission signal output unit that outputs the permission signal synchronized with the periodic signal to the internal power supply circuit, when a mode signal indicating any mode of the normal operation mode and the standby mode and the periodic signal are input and the input mode signal indicates the standby mode.

Abstract: A semiconductor device includes a bonding option pad, an internal power supply, and a MOS transistor. The bonding option pad is selectively wire-bonded to two voltage supply portions through which external power supply voltages with different power supply potentials are supplied from an external power supply. The internal power supply is caused to generate a pre-specified internal power supply voltage. The MOS transistor stabilizes an output level of the internal power supply voltage. The source and drain of the MOS transistor are shorted together and connected to the bonding option pad, and the gate there.