Patents by Inventor Akihiro Horiguchi

Akihiro Horiguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7061862
    Abstract: An inter-network relay unit is provided that is capable of simultaneously achieving guaranteed minimum bandwidth and priority control (including relay priority, discard priority, delay priority, etc.). A rate controller outputs relatively high priority packets from priority queues as guaranteed traffic based on guaranteed bandwidth for each link. Relatively low priority packets left in the priority queues are marked for preferential discard and output as best-effort traffic by an aging timer. When an output port is congested, an output queue portion discards only the marked packets. Thus, traffic having a plurality of relay priorities can use the guaranteed minimum bandwidth effectively and the guaranteed minimum bandwidth can be secured, irrespective of change in traffic volume for each relay priority level.
    Type: Grant
    Filed: December 11, 2001
    Date of Patent: June 13, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akihiro Horiguchi, Takahiro Murono
  • Patent number: 6781994
    Abstract: This invention has as its object to provide an ATM relay device which attains high-speed, large-capacity packet relaying by distributing the load on an IP forwarding unit without having to improve the operation speed, processing performance, and the like of an IP forwarding function. This invention has an ATM switch core (111) for distributing input ATM cells to corresponding ones of a plurality of output ports on the basis of their destination information. A plurality of IP forwarding units (120-1 to 120-n), which are provided in correspondence with the respective output ports of the ATM switch core (111) and have unique forwarding processing functions, execute predetermined forwarding processes for packets obtained by reassembling ATM cells input via the respective output ports.
    Type: Grant
    Filed: August 24, 1999
    Date of Patent: August 24, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuo Nogami, Akihiro Horiguchi, Keitaro Hirai, Kazuaki Mori, Takashi Ikeda, Junichi Takahashi, Tohru Kishigami, Masanori Watanabe
  • Publication number: 20020071387
    Abstract: An inter-network relay unit is provided that is capable of simultaneously achieving guaranteed minimum bandwidth and priority control (including relay priority, discard priority, delay priority, etc.). A rate controller outputs relatively high priority packets from priority queues as guaranteed traffic based on guaranteed bandwidth for each link. Relatively low priority packets left in the priority queues are marked for preferential discard and output as best-effort traffic by an aging timer. When an output port is congested, an output queue portion discards only the marked packets. Thus, traffic having a plurality of relay priorities can use the guaranteed minimum bandwidth effectively and the guaranteed minimum bandwidth can be secured, irrespective of change in traffic volume for each relay priority level.
    Type: Application
    Filed: December 11, 2001
    Publication date: June 13, 2002
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Akihiro Horiguchi, Takahiro Murono
  • Patent number: 6310282
    Abstract: A photovoltaic conversion element comprising, a first transparent electrode, a transparent semiconductor layer disposed on the first transparent electrode, a sensitizing dye adsorption portion which is disposed on the surface of the transparent semiconductor layer, a carrier transport layer formed on the sensitizing dye adsorption portion, and a second transparent electrode disposed on the carrier transport layer, wherein the sensitizing dye adsorption portion comprises sensitizing dyes of plural kinds of color, which are adsorbed on a plurality of surface regions of the semiconductor layer.
    Type: Grant
    Filed: March 16, 2000
    Date of Patent: October 30, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masatoshi Sakurai, Katsuyuki Naito, Akihiro Horiguchi, Hiroyasu Sumino, Maki Yonetsu
  • Patent number: 6110596
    Abstract: Disclosed are a circuit substrate which comprises a silicon nitride ceramic plate 1 having a thermal conductivity at room temperature of 80 W/mK or more and a metal plate 2 joined to the silicon nitride ceramic plate 1 through a glass layer 3, and a semiconductor device in which the circuit substrate is mounted.
    Type: Grant
    Filed: September 26, 1996
    Date of Patent: August 29, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mitsuo Kasori, Akihiro Horiguchi, Hiroyasu Sumino, Fumio Ueno
  • Patent number: 6107638
    Abstract: Disclosed is a silicon nitride circuit substrate, a manufacturing procee thereof, and a semiconductor device therewith. The circuit substrate comprises: a silicon nitride substrate; a metal circuit plate; and a intermediate layer being interposed between the silicon nitride board and the metal circuit plate for joining the silicon nitride substrate and the metal circuit plate, and having a compound containing an aluminum oxide component. The concentration of the aluminum oxide component in the intermediate layer is higher in the side of the metal circuit plate than in the side of the silicon nitride board.
    Type: Grant
    Filed: March 16, 1998
    Date of Patent: August 22, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroyasu Sumino, Akihiro Horiguchi, Mitsuo Kasori, Fumio Ueno
  • Patent number: 6086990
    Abstract: Disclosed are a high thermal conductivity silicon nitride circuit substrate which comprises a silicon nitride ceramic plate having a thermal conductivity at 25.degree. C. of 60 W/m.multidot.K or more and a metal circuit plate joined to the silicon nitride ceramic plate through an intermediate layer containing oxygen and at least one element selected from the group consisting of titanium, zirconium, hafnium, niobium and aluminum, and a semiconductor device using the same.
    Type: Grant
    Filed: September 26, 1996
    Date of Patent: July 11, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroyasu Sumino, Akihiro Horiguchi, Mitsuo Kasori, Fumio Ueno
  • Patent number: 6013356
    Abstract: A circuit board having at least one insulator layer and at least one conductor layer which includes at least one of the whole insulator layers in a sintered body containing .beta.-Si.sub.3 N.sub.4 as a main component and at least one element selected from the group consisting of a rare earth element and an alkaline earth element, and at least one of the whole conductor layers contains at least one element selected from the group of IVb, Vb and VIb group of the periodic table, and at least one element selected from the group of a rare earth element and an alkaline earth element, and a Si element.
    Type: Grant
    Filed: September 26, 1996
    Date of Patent: January 11, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akihiro Horiguchi, Hiroyasu Sumino, Mitsuo Kasori, Fumio Ueno
  • Patent number: 5641718
    Abstract: Disclosed is a sintered aluminum nitride composition and a circuit substrate for use in semiconductor device. The sintered aluminum nitride composition comprises: aluminum nitride; a first component given by a compound containing an element which is selected from the group consisting of alkaline earth elements and group IIIa elements of the periodic table; a second component made of either a simple silicon or a silicon-containig compound; and a third component made of either a simple manganese or a manganese-containing compound. The circuit substrate has an insulating layer which is compoesd of the above-described sintered aluminum nitride composition, and an electrically conductive layer containing an electrically conductive material and the same components as those of the insulating layer.
    Type: Grant
    Filed: August 30, 1995
    Date of Patent: June 24, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akihiro Horiguchi, Katsuyoshi Oh-Ishi, Mitsuo Kasori, Hiroyasu Sumino, Fumio Ueno, Jun Monma, Kazuo Kimura
  • Patent number: 5616956
    Abstract: Disclosed is a circuit substrate and a semiconductor device to which the circuit substrate is applied. The circuit substrate has an insulating layer and an electrically conductive layer. The insulating layer is composed of a sintered aluminum nitride composition containing: aluminum nitride; a first component given by a compound containing an element which is selected from the group consisting of group IIa elements and group IIIa elements of the periodic table; a second component given by either a simple boron or a boron compound; and a third component give by either a simple manganese or a manganese compound. The electrically conductive layer contains: a conductive component given by a metal or an electrically conductive compound for exhibiting electric conductivity; aluminum nitride; the first component; the second component; and the third component.
    Type: Grant
    Filed: September 7, 1995
    Date of Patent: April 1, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akihiro Horiguchi, Jun Monma, Kazuo Kimura, Katsuyoshi Oh-Ishi, Fumio Ueno, Mitsuo Kasori, Hiroyasu Sumino
  • Patent number: 5541926
    Abstract: An ATM cell assembly and disassembly device capable of flexibly dealing with various data speeds on STM and ATM sides, and preventing the buffer overflow. In the ATM cell assembly device, the data stored in the buffer are outputted when an amount of the stored data becomes not less than a prescribed data amount sufficient for loading a payload section of each ATM cell, and the ATM cell flow is obtained from the ATM cells assembled from the data outputted from the buffer and empty cells. The buffer can be allowed to output the stored data only when the output permission signal issued in accordance with usage parameter control (UPC) parameters determined at a time of call set up is received. In the ATM cell disassembly device, the output data are stored into the buffer when a currently remaining capacity of the buffer becomes not less than an amount of data loaded in a payload section of each ATM cell, and the STM signals are obtained from the output data outputted from the buffer.
    Type: Grant
    Filed: October 4, 1993
    Date of Patent: July 30, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takeshi Saito, Akihiro Horiguchi, Muneyuki Suzuki, Keiji Tsunoda
  • Patent number: 5500395
    Abstract: Disclosed is an aluminum nitride sintered body which has a high thermal conductivity and a high strength and which can be manufactured through low-temperature, short-time sintering. This aluminum nitride sintered body has an average grain size of aluminum nitride grains of 2 .mu.m or less, a thermal conductivity of 80 W/m.K or more, and a relative density of 98% or more.
    Type: Grant
    Filed: October 11, 1994
    Date of Patent: March 19, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Fumio Ueno, Mitsuo Kasori, Akihiro Horiguchi, Katsuyoshi Oh-Ishi
  • Patent number: 5409869
    Abstract: Disclosed is an aluminum nitride sintered body which has a high thermal conductivity and a high strength and which can be manufactured through low-temperature, short-time sintering. This aluminum nitride sintered body has an average grain size of aluminum nitride grains of 2 .mu.m or less, a thermal conductivity of 80 W/m.K or more, and a relative density of 98% or more.
    Type: Grant
    Filed: November 18, 1993
    Date of Patent: April 25, 1995
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Fumio Ueno, Mitsuo Kasori, Akihiro Horiguchi, Katsuyoshi Oh-Ishi
  • Patent number: 5286927
    Abstract: Disclosed is a method of manufacturing a circuit board comprising an insulating substrate and a conductor pattern of a low resistivity which can be prevented from being peeled off the substrate by a thermal stress. The method comprises the step of forming an insulating layer on an insulating substrate, the insulating layer being provided with a groove having a depth of at least 20 .mu.m and shaped like a conductor pattern which is to be formed later, the step of filling the groove of the insulating layer with a paste composition consisting of a powdery material capable of forming an electrically conductive metal, a fine particles having a thermal expansion coefficient smaller than that of the electrically conductive metal, the fine particles being used in an amount of 0.
    Type: Grant
    Filed: October 13, 1992
    Date of Patent: February 15, 1994
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Fumio Ueno, Mitsuo Kasori, Yoshiko Goto, Akihiro Horiguchi
  • Patent number: 5284537
    Abstract: In an aluminum nitride structure, a plurality of aluminum nitride regions having different purities are integrally formed to satisfy a predetermined positional relationship, and neighboring regions are brought into direct contact with each other to form an abrupt junction therebetween. Therefore, the aluminum nitride structure has anisotropy in physical properties such as a thermal conductivity, a light transmittance, and a strength.
    Type: Grant
    Filed: December 10, 1992
    Date of Patent: February 8, 1994
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mitsuo Kasori, Akihiro Horiguchi, Yoshiko Goto, Fumio Ueno
  • Patent number: 5280850
    Abstract: According to this invention, there is provided a method of manufacturing a highly reliable circuit board in which a copper member is strongly, directly bonded to a substrate made of an aluminum nitride sintered body, thereby obtaining high peel strength. The method of manufacturing the circuit board includes the steps of bringing a copper member containing 100 to 1,000 ppm of oxygen into contact with an oxide layer having a thickness of 0.1 to 5 .mu.m formed on a surface of a substrate made of an aluminum nitride sintered body, and heating the substrate in an inert gas atmosphere containing 1 to 100 ppm of oxygen at a temperature not more than a temperature corresponding to a liquidus including a pure copper melting point of a hypoeutectic region of a two-component phase diagram of Cu-Cu.sub.
    Type: Grant
    Filed: October 16, 1992
    Date of Patent: January 25, 1994
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akihiro Horiguchi, Mitsuo Kasori, Fumio Ueno, Hiroshi Komorita
  • Patent number: 5204080
    Abstract: An aluminum nitride structure is prepared by placing an oxygen-trapping substance at at least one position on an aluminum nitride substrate having a first concentration of solution oxygen, and heating the resultant structure in a non-oxidizing atmosphere to locally reduce the first concentration of solution oxygen in said aluminum nitride substrate under said oxygen-trapping substance to a second concentration of solution oxygen by trapping the solution oxygen in the oxygen-trapping substance, thereby forming an aluminum nitride structure in which at least one region of the aluminum nitride structure corresponding to the position of said oxygen-trapping substance, which position has said second oxygen concentration, is integrally formed with aluminum nitride regions having said first concentration of solution oxygen. The aluminum nitride structure of the present invention exhibits anisotropic physical properties.
    Type: Grant
    Filed: June 29, 1990
    Date of Patent: April 20, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mitsuo Kasori, Akihiro Horiguchi, Yoshiko Goto, Fumio Ueno
  • Patent number: 5184399
    Abstract: Disclosed is a method of manufacturing a circuit board comprising an insulating substrate and a conductor pattern of a low resistivity which can be prevented from being peeled off the substrate by a thermal stress. The method comprises the step of forming an insulating layer on an insulating substrate, the insulating layer being provided with a groove having a depth of at least 20 .mu.m and shaped like a conductor pattern which is to be formed later, the step of filling the groove of the insulating layer with a paste composition consisting of a powdery material capable of forming an electrically conductive metal, a fine particles having a thermal expansion coefficient smaller than that of the electrically conductive metal, the fine particles being used in an amount of 0.
    Type: Grant
    Filed: June 28, 1991
    Date of Patent: February 9, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Fumio Ueno, Mitsuo Kasori, Yoshiko Goto, Akihiro Horiguchi
  • Patent number: 5182540
    Abstract: A resistor element includes a hollow cylindrical sintered body and a pair of electrodes formed on the upper and lower surfaces of the sintered body. The sintered body contains ferrite as a main constituent and contains 0.05 to 10% by volume of an insulator phase formed at the crystal grain boundary of the ferrite crystals. An insulating layer is formed to cover the side surface of the sintered body. The sintered body contains an oxide material selected from the group consisting of 0.005 to 2.0% by weight of bismuth oxide calculated in terms of Bi.sub.2 O.sub.3, 0.01 to 3.0% by weight and 0.005 to 2.0% by weight of silicon oxide and aluminum oxide calculated in terms of SiO.sub.2 and Al.sub.2 O.sub.3 respectively, and 0.01 to 3.5% by weight and 0.001 to 1.6% by weight of silicon oxide and calcium oxide calculated in terms of SiO.sub.2 and CaO, respectively.
    Type: Grant
    Filed: February 28, 1991
    Date of Patent: January 26, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Naoki Shuto, Fumio Ueno, Yoshiko Goto, Akihiro Horiguchi, Mitsuo Kasori, Motomasa Imai
  • Patent number: 5176309
    Abstract: According to this invention, there is provided a method of manufacturing a highly reliable circuit board in which a copper member is strongly, directly bonded to a substrate made of an aluminum nitride sintered body, thereby obtaining high peel strength. The method of manufacturing the circuit board includes the steps of bringing a copper member containing 100 to 1,000 ppm of oxygen into contact with an oxide layer having a thickness of 0.1 to 5 .mu.m formed on a surface of a substrate made of an aluminum nitride sintered body, and heating the substrate in an inert gas atmosphere containing 1 to 100 ppm of oxygen at a temperature not more than a temperature corresponding to a liquidus including a pure copper melting point of a hypoeutectic region of a two-component phase diagram of Cu-Cu.sub.
    Type: Grant
    Filed: May 22, 1991
    Date of Patent: January 5, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akihiro Horiguchi, Mitsuo Kasori, Fumio Ueno, Hiroshi Komorita, Mitsuyoshi Endo