Patents by Inventor Akihiro IEDA

Akihiro IEDA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Laminated inductor element and manufacturing method thereof
    Patent number: 8810352
    Abstract: In a laminated inductor element, outer electrodes and terminal electrodes are electrically connected by via holes, internal wiring lines, and end surface electrodes. The via holes on an upper surface side are provided immediately under the outer electrodes and in a non-magnetic ferrite layer. The via holes on a lower surface side are provided immediately above the terminal electrodes and in a non-magnetic ferrite layer. Since outermost layers are defined by the non-magnetic ferrite layers, a parasitic inductance is not increased, even if the outermost layers are provided with the via holes. In this case, the internal wiring lines are not routed on a surface of the element. Therefore, there is no complication of a wiring pattern, and it is possible to prevent an increase in a mounting area of the element.
    Type: Grant
    Filed: July 31, 2013
    Date of Patent: August 19, 2014
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Tomoya Yokoyama, Takako Sato, Akihiro Ieda, Shigetoshi Hayashi, Hirokazu Yazaki
  • LAMINATED INDUCTOR ELEMENT AND MANUFACTURING METHOD THEREOF
    Publication number: 20130314190
    Abstract: In a laminated inductor element, outer electrodes and terminal electrodes are electrically connected by via holes, internal wiring lines, and end surface electrodes. The via holes on an upper surface side are provided immediately under the outer electrodes and in a non-magnetic ferrite layer. The via holes on a lower surface side are provided immediately above the terminal electrodes and in a non-magnetic ferrite layer. Since outermost layers are defined by the non-magnetic ferrite layers, a parasitic inductance is not increased, even if the outermost layers are provided with the via holes. In this case, the internal wiring lines are not routed on a surface of the element. Therefore, there is no complication of a wiring pattern, and it is possible to prevent an increase in a mounting area of the element.
    Type: Application
    Filed: July 31, 2013
    Publication date: November 28, 2013
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Tomoya YOKOYAMA, Takako SATO, Akihiro IEDA, Shigetoshi HAYASHI, Hirokazu YAZAKI