Abstract: An operation method of a semiconductor storage device including a first memory die is provided. The first memory die includes a first memory plane including a plurality of first memory blocks, a second memory plane including a plurality of second memory blocks. The method includes starting a first write sequence with respect to one of the first memory blocks in response to a first command set designating the one of the first memory blocks and starting a second write sequence with respect to one of the second memory blocks in response to a second command set designating the one of the second memory blocks. At least part of the second write sequence is performed while the first write sequence is being performed.

Abstract: A semiconductor memory device according to an embodiment includes a plurality of planes including a plurality of blocks each being a set of memory cells, and a sequencer configured to execute a first operation and a second operation shorter than the first operation. Upon receiving a first command set that instructs execution of the first operation, the sequencer is configured to execute the first operation. Upon receiving a second command set that instructs execution of the second operation while the first operation is being executed, the sequencer is configured to suspend the first operation and execute the second operation or execute the second operation in parallel with the first operation, based on an address of a block that is a target of the first operation and an address of a block that is a target of the second operation.

Abstract: A semiconductor memory device according to an embodiment includes a plurality of planes including a plurality of blocks each being a set of memory cells, and a sequencer configured to execute a first operation and a second operation shorter than the first operation. Upon receiving a first command set that instructs execution of the first operation, the sequencer is configured to execute the first operation. Upon receiving a second command set that instructs execution of the second operation while the first operation is being executed, the sequencer is configured to suspend the first operation and execute the second operation or execute the second operation in parallel with the first operation, based on an address of a block that is a target of the first operation and an address of a block that is a target of the second operation.

Abstract: An operation method of a semiconductor storage device including a first memory die is provided. The first memory die includes a first memory plane including a plurality of first memory blocks, a second memory plane including a plurality of second memory blocks. The method includes starting a first write sequence with respect to one of the first memory blocks in response to a first command set designating the one of the first memory blocks and starting a second write sequence with respect to one of the second memory blocks in response to a second command set designating the one of the second memory blocks. At least part of the second write sequence is performed while the first write sequence is being performed.

Abstract: A semiconductor memory device according to an embodiment includes a plurality of planes including a plurality of blocks each being a set of memory cells, and a sequencer configured to execute a first operation and a second operation shorter than the first operation. Upon receiving a first command set that instructs execution of the first operation, the sequencer is configured to execute the first operation. Upon receiving a second command set that instructs execution of the second operation while the first operation is being executed, the sequencer is configured to suspend the first operation and execute the second operation or execute the second operation in parallel with the first operation, based on an address of a block that is a target of the first operation and an address of a block that is a target of the second operation.

Abstract: A semiconductor storage device includes a first memory die. The first memory die includes a first memory plane including a plurality of first memory blocks, a second memory plane including a plurality of second memory blocks, a first sequencer, and a second sequencer. The first sequencer is configured to start a first write sequence with respect to one of the first memory blocks in response to a first command set designating the one of the first memory blocks if no write sequence is being performed by the first sequencer. The second sequencer is configured to start a second write sequence with respect to one of the second memory blocks in response to a second command set designating the one of the second memory blocks if the first sequencer is performing the first write sequence and no write sequence is being performed by the second sequencer.

Abstract: A semiconductor memory device according to an embodiment includes a plurality of planes including a plurality of blocks each being a set of memory cells, and a sequencer configured to execute a first operation, and a second operation shorter than the first operation. Upon receiving a first command set that instructs execution of the first operation, the sequencer is configured to execute the first operation. Upon receiving a second command set that instructs execution of the second operation while the first operation is being executed, the sequencer is configured to suspend the first operation and execute the second operation or execute the second operation in parallel with the first operation, based on an address of a block that is a target of the first operation and an address of a block that is a target of the second operation.

Abstract: A semiconductor storage device includes a first memory die. The first memory die includes a first memory plane including a plurality of first memory blocks, a second memory plane including a plurality of second memory blocks, a first sequencer, and a second sequencer. The first sequencer is configured to start a first write sequence with respect to one of the first memory blocks in response to a first command set designating the one of the first memory blocks if no write sequence is being performed by the first sequencer. The second sequencer is configured to start a second write sequence with respect to one of the second memory blocks in response to a second command set designating the one of the second memory blocks if the first sequencer is performing the first write sequence and no write sequence is being performed by the second sequencer.

Abstract: A semiconductor memory device includes a first memory cell, a second memory cell, and a first wiring and a second wiring electrically connected to the first memory cell and the second memory cell. In a write operation, a program operation starts at a first timing and a supply of a write pass voltage starts at a second timing. When a first command is received in a first period between the first timing and the second timing, the write operation is interrupted before the supply of the write pass voltage starts.

Abstract: A semiconductor storage device includes first and second planes each including a plurality of memory cells, an input/output circuit configured to receive data to be written in the memory cells from a controller, and a control circuit. The first plane includes a first sense amplifier circuit electrically connected to a first memory cell of the first plane and a first latch circuit connected in series between the input/output circuit and the first sense amplifier circuit. The control circuit is configured to carry out a first write operation on the first memory cell using the first latch circuit in response to a first command, and while carrying out the first write operation on the first memory cell, accept a second command to carry out a second write operation on a second memory cell of the second plane before use of the first latch circuit during the first write operation has ended.

Abstract: A semiconductor memory device according to an embodiment includes a plurality of planes including a plurality of blocks each being a set of memory cells, and a sequencer configured to execute a first operation, and a second operation shorter than the first operation. Upon receiving a first command set that instructs execution of the first operation, the sequencer is configured to execute the first operation. Upon receiving a second command set that instructs execution of the second operation while the first operation is being executed, the sequencer is configured to suspend the first operation and execute the second operation or execute the second operation in parallel with the first operation, based on an address of a block that is a target of the first operation and an address of a block that is a target of the second operation.

Abstract: A semiconductor memory device includes a first memory cell, a second memory cell, and a first wiring and a second wiring electrically connected to the first memory cell and the second memory cell. In a write operation, a program operation starts at a first timing and a supply of a write pass voltage starts at a second timing. When a first command is received in a first period between the first timing and the second timing, the write operation is interrupted before the supply of the write pass voltage starts.

Abstract: According to one embodiment, a semiconductor memory device includes: planes each including a memory cell array including memory cells; a comparator configured to, when suspending a write operation and executing a read operation, compare a first plane address corresponding to the write operation with a second plane address corresponding to the read operation; and a controller configured to suspend the write operation and execute the read operation. The controller is configured to, based on an output signal from the comparator, execute the first read operation when the first and second plane addresses match, and execute the second read operation when the first and second plane addresses differ.

Abstract: A semiconductor storage device includes first and second planes each including a plurality of memory cells, an input/output circuit configured to receive data to be written in the memory cells from a controller, and a control circuit. The first plane includes a first sense amplifier circuit electrically connected to a first memory cell of the first plane and a first latch circuit connected in series between the input/output circuit and the first sense amplifier circuit. The control circuit is configured to carry out a first write operation on the first memory cell using the first latch circuit in response to a first command, and while carrying out the first write operation on the first memory cell, accept a second command to carry out a second write operation on a second memory cell of the second plane before use of the first latch circuit during the first write operation has ended.

Abstract: According to one embodiment, a semiconductor memory device includes: planes each including a memory cell array including memory cells; a comparator configured to, when suspending a write operation and executing a read operation, compare a first plane address corresponding to the write operation with a second plane address corresponding to the read operation; and a controller configured to suspend the write operation and execute the read operation. The controller is configured to, based on an output signal from the comparator, execute the first read operation when the first and second plane addresses match, and execute the second read operation when the first and second plane addresses differ.

Abstract: A semiconductor storage device includes first and second planes each including a plurality of memory cells, an input/output circuit configured to receive data to be written in the memory cells from a controller, and a control circuit. The first plane includes a first sense amplifier circuit electrically connected to a first memory cell of the first plane and a first latch circuit connected in series between the input/output circuit and the first sense amplifier circuit. The control circuit is configured to carry out a first write operation on the first memory cell using the first latch circuit in response to a first command, and while carrying out the first write operation on the first memory cell, accept a second command to carry out a second write operation on a second memory cell of the second plane before use of the first latch circuit during the first write operation has ended.

Abstract: A semiconductor storage device includes first and second planes each including a plurality of memory cells, an input/output circuit configured to receive data to be written in the memory cells from a controller, and a control circuit. The first plane includes a first sense amplifier circuit electrically connected to a first memory cell of the first plane and a first latch circuit connected in series between the input/output circuit and the first sense amplifier circuit. The control circuit is configured to carry out a first write operation on the first memory cell using the first latch circuit in response to a first command, and while carrying out the first write operation on the first memory cell, accept a second command to carry out a second write operation on a second memory cell of the second plane before use of the first latch circuit during the first write operation has ended.

Abstract: According to one embodiment, a memory device includes a memory cell array configured to store data and a clock generator configured to generate a clock signal, the memory device outputs data held in the memory cell array in accordance with a timing of the clock signal, and the clock generator generates the clock signal with a substantially constant gradient each time a power supply is turned on.

Abstract: A NAND type flash memory for erasing data every block including plural memory cell transistors that are provided every block and have floating gates formed through first gate insulating film above a well formed in a semiconductor substrate and control gates formed through second gate insulating film above the floating gates, data in the memory cell transistors being rewritable by controlling charge amounts accumulated in the floating gates, and a row decoder having a plurality of MOS transistors having drains that are respectively connected to corresponding word lines connected to the control gates of the plurality of memory cell transistors, the row decoder controlling gate and source voltages of the MOS transistors.

Abstract: A nonvolatile semiconductor memory device according to an embodiment includes: a memory cell array including a plurality of memory cells selected by word lines and bit lines, each memory cell being capable of storing N-bit data, a set of n-th bits of a plurality of memory cells selected by one of the word lines constituting an n-th physical page, and a predetermined number of the bit lines constituting one column; and a data writing unit that divides each of first to N-th input data of the length of the physical page or less input from the outside into unit data of the length of the column, changes at least a portion of the order of unit data of the first to N-th input data of a predetermined column in the predetermined column before data writing, and performs writing.